-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 23:20:57 05/02/2016 -- Design Name: -- Module Name: C:/Users/User/Desktop/Final Year Project/selectsig/selectsig_tb.vhd -- Project Name: selectsig -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: selectsig -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY select_sig_tb IS END select_sig_tb; ARCHITECTURE behavior OF select_sig_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT select_sig PORT( clock : IN std_logic; s0 : IN std_logic; s1 : IN std_logic; s2 : IN std_logic; sig : OUT std_logic_vector(2 downto 0) ); END COMPONENT; --Inputs signal clock : std_logic := '0'; signal s0 : std_logic := '0'; signal s1 : std_logic := '0'; signal s2 : std_logic := '0'; --Outputs signal sig : std_logic_vector(2 downto 0); -- Clock period definitions constant clock_period : time := 20 ns; --50MHz BEGIN -- Instantiate the Unit Under Test (UUT) uut: select_sig PORT MAP ( clock => clock, s0 => s0, s1 => s1, s2 => s2, sig => sig ); -- Clock process definitions clock_process :process begin clock <= '1'; wait for clock_period/2; clock <= '0'; wait for clock_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100ms. wait for 20 ns; s0 <= '1'; wait for 20 ns; s1 <= '1'; wait for 20 ns; s2 <= '1'; wait; end process; END;