*** Running vivado
    with args -log Count_code.vdi -applog -m32 -messageDb vivado.pb -mode batch -source Count_code.tcl -notrace

INFO: [Common 17-701] A license check has taken more than 10 seconds to complete. This may indicate that there is a performance issue with one or more license servers listed in XILINXD_LICENSE_FILE or LM_LICENSE_FILE, or that the license servers are just not responding at all. Try setting the FLEXLM_DIAGNOSTICS environment variable to 3 and running Vivado again to get more information.

****** Vivado v2014.2
  **** SW Build 932637 on Wed Jun 11 13:24:38 MDT 2014
  **** IP Build 924643 on Fri May 30 09:20:16 MDT 2014
    ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

source Count_code.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.2
Loading clock regions from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2014.2/data/parts/xilinx/zynq/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2014.2/data\parts/xilinx/zynq/zynq/xc7z010/clg400/Package.xml
Loading io standards from C:/Xilinx/Vivado/2014.2/data\./parts/xilinx/zynq/IOStandards.xml
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
Parsing XDC File [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc]
WARNING: [Vivado 12-180] No cells matched 'CLK'. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:1]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:1]
WARNING: [Vivado 12-180] No cells matched 'updown'. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:2]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:2]
WARNING: [Vivado 12-180] No cells matched 'Q[0]'. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:3]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:3]
WARNING: [Vivado 12-180] No cells matched 'Q[1]'. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:4]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:4]
WARNING: [Vivado 12-180] No cells matched 'Q[2]'. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:5]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:5]
WARNING: [Vivado 12-180] No cells matched 'Q[3]'. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:6]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:6]
WARNING: [Vivado 12-180] No cells matched 'reset'. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:7]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc:7]
Finished Parsing XDC File [D:/XILINX_LABS/LAB_zed/project_14/project_14.srcs/constrs_1/new/321.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 499.316 ; gain = 158.891
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.187 . Memory (MB): peak = 500.469 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget

INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: ed58d1b8

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 31 cells.
Phase 2 Constant Propagation | Checksum: 1af96c4f3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 54 unconnected nets.
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 3 Sweep | Checksum: 105535999

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 765.840 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 105535999

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 765.840 ; gain = 0.000
Implement Debug Cores | Checksum: ed58d1b8
Logic Optimization | Checksum: ed58d1b8

Starting Power Optimization Task
INFO: [Pwropt 34-132] Will skip clock gating for clocks with period < 3.13 ns.
Ending Power Optimization Task | Checksum: 105535999

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 765.840 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
22 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 765.840 ; gain = 266.523
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Runtime Estimator
Phase 1 Placer Runtime Estimator | Checksum: cba5f51e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2 Placer Initialization

Phase 2.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.1 Mandatory Logic Optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 2.1.1 Mandatory Logic Optimization | Checksum: 00000000

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.2 Build Super Logic Region (SLR) Database
Phase 2.1.2 Build Super Logic Region (SLR) Database | Checksum: 00000000

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.3 Add Constraints
Phase 2.1.3 Add Constraints | Checksum: 00000000

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.4 Build Shapes/ HD Config

Phase 2.1.4.1 Build Macros
Phase 2.1.4.1 Build Macros | Checksum: 094593ef

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 2.1.4 Build Shapes/ HD Config | Checksum: 094593ef

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.5 IO Placement/ Clock Placement/ Build Placer Device

Phase 2.1.5.1 Pre-Place Cells
Phase 2.1.5.1 Pre-Place Cells | Checksum: 00000000

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 765.840 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 2.1.5.2 IO & Clk Clean Up
Phase 2.1.5.2 IO & Clk Clean Up | Checksum: 00000000

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.234 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.5.3 Implementation Feasibility check On IDelay
Phase 2.1.5.3 Implementation Feasibility check On IDelay | Checksum: 00000000

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.234 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.5.4 Commit IO Placement
Phase 2.1.5.4 Commit IO Placement | Checksum: 663e60d8

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.234 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 2.1.5 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6f83f4c7

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.234 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.6 Build Placer Netlist Model

Phase 2.1.6.1 Place Init Design
Phase 2.1.6.1 Place Init Design | Checksum: 15a77596c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 2.1.6 Build Placer Netlist Model | Checksum: 15a77596c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 2.1.7 Constrain Clocks/Macros

Phase 2.1.7.1 Constrain Global/Regional Clocks
Phase 2.1.7.1 Constrain Global/Regional Clocks | Checksum: 15a77596c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 2.1.7 Constrain Clocks/Macros | Checksum: 15a77596c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 2.1 Placer Initialization Core | Checksum: 15a77596c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 2 Placer Initialization | Checksum: 15a77596c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 3 Global Placement
Phase 3 Global Placement | Checksum: dc3f185a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.484 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 4 Detail Placement

Phase 4.1 Commit Multi Column Macros
Phase 4.1 Commit Multi Column Macros | Checksum: dc3f185a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.484 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 4.2 Commit Most Macros & LUTRAMs
Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 1b933654e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.500 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 4.3 Area Swap Optimization
Phase 4.3 Area Swap Optimization | Checksum: 11b473700

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 4.4 Commit Small Macros & Core Logic
Phase 4.4 Commit Small Macros & Core Logic | Checksum: 18021383d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.625 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 4.5 Re-assign LUT pins
Phase 4.5 Re-assign LUT pins | Checksum: 18021383d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 4 Detail Placement | Checksum: 18021383d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 5 Post Placement Optimization and Clean-Up

Phase 5.1 PCOPT Shape updates
Phase 5.1 PCOPT Shape updates | Checksum: 18021383d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 5.2 Post Placement Cleanup
Phase 5.2 Post Placement Cleanup | Checksum: 18021383d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 5.3 Placer Reporting
Phase 5.3 Placer Reporting | Checksum: 18021383d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 765.840 ; gain = 0.000

Phase 5.4 Final Placement Cleanup
Phase 5.4 Final Placement Cleanup | Checksum: 1dc49e18b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 765.840 ; gain = 0.000
Phase 5 Post Placement Optimization and Clean-Up | Checksum: 1dc49e18b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 765.840 ; gain = 0.000
Ending Placer Task | Checksum: f6b648ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.656 . Memory (MB): peak = 765.840 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
29 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.391 . Memory (MB): peak = 765.840 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 765.840 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Starting Route Task

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 9b9e6d02

Time (s): cpu = 00:00:27 ; elapsed = 00:00:24 . Memory (MB): peak = 859.547 ; gain = 93.707

Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 1a5798351

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 4f1ac00d

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 1bf78a19

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258
Phase 4 Rip-up And Reroute | Checksum: 1bf78a19

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258

Phase 5 Post Hold Fix
Phase 5 Post Hold Fix | Checksum: 1bf78a19

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258

Phase 6 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.013795 %
  Global Horizontal Routing Utilization  = 0.0356158 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 6.30631%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 4.5045%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions.
Phase 6 Route finalize | Checksum: 1bf78a19

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258

Phase 7 Verifying routed nets

 Verification completed successfully
Phase 7 Verifying routed nets | Checksum: 1bf78a19

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258

Phase 8 Depositing Routes
Phase 8 Depositing Routes | Checksum: f7982e5c

Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258
INFO: [Route 35-16] Router Completed Successfully
Ending Route Task | Checksum: f7982e5c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:25 . Memory (MB): peak = 864.098 ; gain = 98.258

Routing Is Done.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:26 . Memory (MB): peak = 864.098 ; gain = 98.258
INFO: [Common 17-83] Releasing license: Implementation
37 Infos, 7 Warnings, 7 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 864.098 ; gain = 98.258
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.282 . Memory (MB): peak = 864.098 ; gain = 0.000
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file D:/XILINX_LABS/LAB_zed/project_14/project_14.runs/impl_1/Count_code_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Constraints type: SDC.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Power 33-232] No user defined clocks was found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 7 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Q[3:0], clk, updown, reset.
ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 7 out of 7 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: Q[3:0], clk, updown, reset.
INFO: [Vivado 12-3199] DRC finished with 2 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

    while executing
"write_bitstream -force Count_code.bit "
INFO: [Common 17-206] Exiting Vivado at Mon Apr 11 15:03:31 2016...