module motor(clk,reset,a,b);
input clk,reset,a;
output reg b;

always@(posedge clk)
begin
if(reset==1'b1)
begin
b=0;
end
else
if(a==1)
begin
b=1;
end
else
begin
b=0;
end
end
endmodule

module motortb();
reg clk,reset,a;
wire b;
motor h1(clk,reset,a,b);
initial 
begin 
clk=1; 
forever 
#5 clk=~clk; 
end 
initial
begin
clk=0;reset=0;a=0;
#2 clk=1;reset=0;a=1;
#2 $stop;
end
endmodule


module top(clk,sw,sw1,led);
input clk,sw,sw1;
output led;
motor h1(clk,sw,sw1,led);
endmodule