start_gui
cd
cd Downloads
cd hdmi_in
cd proj
source ./create_project.tcl
# set proj_name "hdmi-in"
# if {[info exists ::create_path]} {
# 	set dest_dir $::create_path
# } else {
# 	set dest_dir [file normalize [file dirname [info script]]]
# }
# puts "INFO: Creating new project in $dest_dir"
INFO: Creating new project in C:/Users/ar3fin/Downloads/hdmi_in/proj
# cd $dest_dir
# set part "xc7z010clg400-1"
# set brd_part "digilentinc.com:zybo:part0:1.0"
# set origin_dir ".."
# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
# set src_dir $origin_dir/src
# set repo_dir $origin_dir/repo
# create_project $proj_name $dest_dir
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
create_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 710.066 ; gain = 154.219
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects $proj_name]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "part" $part $obj
# set_property "board_part" $brd_part $obj
# set_property "simulator_language" "Mixed" $obj
# set_property "target_language" "VHDL" $obj
# set_property "corecontainer.enable" "0" $obj
# set_property "ip_cache_permissions" "read write" $obj
# set_property "ip_output_repo" "[file normalize "$origin_dir/repo/cache"]" $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#   create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#   create_fileset -constrset constrs_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
# update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/ar3fin/Downloads/hdmi_in/repo'.
update_ip_catalog: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 710.066 ; gain = 0.000
# add_files -quiet $src_dir/hdl
# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
# add_files -fileset constrs_1 -quiet $src_dir/constraints
# if {[string equal [get_runs -quiet synth_1] ""]} {
#   create_run -name synth_1 -part $part -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
# } else {
#   set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
#   set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
# }
# set obj [get_runs synth_1]
# set_property "part" $part $obj
# set_property "steps.synth_design.args.flatten_hierarchy" "none" $obj
# set_property "steps.synth_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.synth_design.args.fsm_extraction" "off" $obj
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#   create_run -name impl_1 -part $part -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
#   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
#   set_property flow "Vivado Implementation 2015" [get_runs impl_1]
# }
# set obj [get_runs impl_1]
# set_property "part" $part $obj
# set_property "steps.opt_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.place_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.route_design.args.directive" "RuntimeOptimized" $obj
# current_run -implementation [get_runs impl_1]
# puts "INFO: Project created:$proj_name"
INFO: Project created:hdmi-in
# set bd_list [glob -nocomplain $src_dir/bd/*/*.bd]
# if {[llength $bd_list] != 0} {
#   add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
#   open_bd_design [glob -nocomplain $src_dir/bd/*/*.bd]
#   set design_name [get_bd_designs]
#   set file "$origin_dir/src/bd/$design_name/$design_name.bd"
#   set file [file normalize $file]
#   set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
#   if { ![get_property "is_locked" $file_obj] } {
#     set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
#   }
#  
#   # Generate the wrapper 
#   set design_name [get_bd_designs]
#   add_files -norecurse [make_wrapper -files [get_files $design_name.bd] -top -force]
# 
#   set obj [get_filesets sources_1]
#   set_property "top" "${design_name}_wrapper" $obj
# }
Adding cell -- digilentinc.com:ip:axi_dynclk:1.0 - axi_dynclk_0
Adding cell -- digilentinc.com:ip:rgb2vga:1.0 - rgb2vga_0
Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_btn
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_led
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_sw
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_video
Adding cell -- xilinx.com:ip:axi_vdma:6.2 - axi_vdma_0
Adding cell -- digilentinc.com:ip:dvi2rgb:1.7 - dvi2rgb_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_processing_system7_0_100M
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_processing_system7_0_150M
Adding cell -- xilinx.com:ip:v_axi4s_vid_out:4.0 - v_axi4s_vid_out_0
Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_0
Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_1
Adding cell -- xilinx.com:ip:v_vid_in_axi4s:4.0 - v_vid_in_axi4s_0
WARNING: [BD 41-1731] Type mismatch between connected pins: /dvi2rgb_0/aPixelClkLckd(undef) and /proc_sys_reset_0/aux_reset_in(rst)
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - m00_data_fifo
Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s01_regslice
Adding cell -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us_df
Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice
Adding cell -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us_df
Successfully read diagram <hdmi_in> from BD file <../src/bd/hdmi_in/hdmi_in.bd>
open_bd_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 798.195 ; gain = 88.129
# set sdk_dir $origin_dir/sdk
# set hw_list [glob -nocomplain $sdk_dir/*hw_platform*]
# if {[llength $hw_list] != 0} {
#   foreach hw_plat $hw_list {
# 	file delete -force $hw_plat
#   }
# }
# set sdk_list [glob -nocomplain $sdk_dir/*]
# set sdk_list [lsearch -inline -all -not -exact $sdk_list "../sdk/.keep"]
# if {[llength $sdk_list] != 0} {
# 	exec xsct -eval "setws -switch ../sdk; importproject ../sdk"
# }
Starting SDK. This could take few seconds... done
'HDMI_IN' will not be imported... [ALREADY EXIST]
'HDMI_IN_bsp' will not be imported... [ALREADY EXIST]
report_ip_status -name ip_status 
make_wrapper -files [get_files C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdmi_in.bd] -top
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Tue Jan 23 22:48:18 2018] Launched synth_1...
Run output will be captured here: C:/Users/ar3fin/Downloads/hdmi_in/proj/hdmi-in.runs/synth_1/runme.log
[Tue Jan 23 22:48:18 2018] Launched impl_1...
Run output will be captured here: C:/Users/ar3fin/Downloads/hdmi_in/proj/hdmi-in.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 856.492 ; gain = 0.000
set_property synth_checkpoint_mode Singular [get_files  C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdmi_in.bd]
generate_target all [get_files  C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdmi_in.bd]
INFO: [BD 41-1662] The design 'hdmi_in.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/m00_regslice/m_axi_rid'(1) to net 'm00_regslice_to_m00_couplers_RID'(6) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/m00_regslice/m_axi_bid'(1) to net 'm00_regslice_to_m00_couplers_BID'(6) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to net 'axi_mem_intercon_M00_AXI_WID'(1) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to net 'axi_mem_intercon_M00_AXI_ARID'(1) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to net 'axi_mem_intercon_M00_AXI_AWID'(1) - Only lower order bits will be connected.
VHDL Output written to : C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdl/hdmi_in.vhd
VHDL Output written to : C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdl/hdmi_in_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_dynclk_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_btn .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_led .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_sw .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_video .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_vdma_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dvi2rgb_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rgb2vga_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_processing_system7_0_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_processing_system7_0_150M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block v_axi4s_vid_out_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block v_tc_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block v_tc_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block v_vid_in_axi4s_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconstant_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s00_couplers/s00_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s01_couplers/s01_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/m00_couplers/m00_data_fifo .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/m00_couplers/m00_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/m00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s00_couplers/auto_us_df .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_mem_intercon/s01_couplers/auto_us_df .
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hw_handoff/hdmi_in.hwh
Generated Block Design Tcl file C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hw_handoff/hdmi_in_bd.tcl
Generated Hardware Definition File C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdl/hdmi_in.hwdef
generate_target: Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 998.723 ; gain = 107.414
export_ip_user_files -of_objects [get_files C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdmi_in.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/Users/ar3fin/Downloads/hdmi_in/src/bd/hdmi_in/hdmi_in.bd]
launch_runs -jobs 2 hdmi_in_synth_1