/* * CAUTION: This file is automatically generated by Xilinx. * Version: HSI 2015.4 * Today is: Tue Oct 31 00:28:13 2017 */ / { amba_pl: amba_pl { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges ; myip32bitadder_0: myip32bitadder@43c00000 { compatible = "xlnx,myip32bitadder-1.0"; reg = <0x43c00000 0x10000>; xlnx,my32bitadder-addr-width = <0x4>; xlnx,my32bitadder-data-width = <0x20>; }; }; };