;------------------------------------------------- ;-- JTAG devices supported by Digilent Adept -- ;-- last modified: 01/17/2017 -- ;-- Copyright 2014, Digilent Inc. -- ;------------------------------------------------- VENDOR{ XILINX 0000002Ah 000000FEh ;used by CoolRunners XILINX 00000092h 00000FFEh ;used by most Xilinx devices XILINX 00000476h 00000FFEh ;used by Xilinx ARM DAP UNKNOWN 00000000h 00000000h ;used for devices of unknown vendor } XILINX{ FAMILY{ ;--- FPGAs XC2S$ 00600000h 0FE00000h XC2S$E 00A00000h 0FE00000h XC3S$ 01400000h 0FE00000h XC3SD$A 06800000h 0FE00000h XC3S$AN 02600000h 0FE00000h XC3S$A 02200000h 0FE00000h XC3S$E 01C00000h 0FE00000h XC6SLX$ 04000000h 0FE00000h XC7A$T 03620000h 0FFF0000h XC7A$T 03630000h 0FFF0000h XC7K$T 03640000h 0FEE0000h XC7VX$T 03660000h 0FFF0000h XC7VX$T 03680000h 0FFE0000h XC7Z$ 03700000h 0FF00000h XCV$ 00600000h 0FE00000h XCV$E 00A00000h 0FE00000h XC2V$ 01000000h 0FE00000h XC2VP$ 01200000h 0FE00000h XC4VFX$ 01E00000h 0FE00000h XC4VLX$ 01600000h 0FE00000h XC4VSX$ 02000000h 0FE00000h XC5VFX$T 03200000h 0FE00000h XC5VLX$ 02800000h 0FE00000h XC5VLX$T 02a00000h 0FE00000h XC5VSX$T 02e00000h 0FE00000h XC5VTX$T 04500000h 0FE00000h XC6VCX$T 042c0000h 0FFE0000h XC6VLX$T 04240000h 0FFE0000h XC6VLX760T 04230000h 0FFF0000h XC6VSX$T 04280000h 0FFE0000h ;--- CPLDs XC95$ 09500000h 0FF00000h XC95$XL 09600000h 0FE00000h XC95$XV 09700000h 0FE00000h XCR3$XL 04800000h 0FE00000h XCR3$XL 04900000h 0FE00000h XC2C$A 06E00000h 0FE00000h XC2C$ 06C00000h 0FE00000h ;--- PROMs (may have longer family IDs) XC18V$ 05020000h 0FFE0000h XCF$P 05050000h 0FFF0000h XCF$S 05040000h 0FFE0000h XCCACE 0a000000h 0FF00000h ;--- Xilinx ARM DAP ARM_DAP 0BA00000h 0FFFF000h UNKNOWN 00000000h 00000000h } ;----------- FPGA devices ----------- XCV${ TYPE = FPGA IRLEN = 5 ALG = 1 COMMANDS{ CFG_OUT 00000004h ;---00100 IDCODE 00000009h ;---01001 CFG_IN 00000005h ;---00101 JSTART 0000000Ch ;---01100 BYPASS 0000001Fh ;---11111 } DEVICES{ 50 00610093h 0FFFFFFFh 100 00614093h 0FFFFFFFh 150 00618093h 0FFFFFFFh 200 0061C093h 0FFFFFFFh 300 00620093h 0FFFFFFFh 400 00628093h 0FFFFFFFh 600 00630093h 0FFFFFFFh 800 00638093h 0FFFFFFFh 1000 00640093h 0FFFFFFFh } } XCV$E{ TYPE = FPGA IRLEN = 5 ALG = 1 COMMANDS{ CFG_OUT 00000004h ;---00100 IDCODE 00000009h ;---01001 CFG_IN 00000005h ;---00101 JSTART 0000000Ch ;---01100 BYPASS 0000001Fh ;---11111 } DEVICES{ 50 00A10093h 0FFFFFFh 100 00A14093h 0FFFFFFh 200 00A1C093h 0FFFFFFh 300 00A20093h 0FFFFFFh 400 00A28093h 0FFFFFFh 405 00C28093h 0FFFFFFh 600 00A30093h 0FFFFFFh 812 00C38093h 0FFFFFFh 1000 00A40093h 0FFFFFFh 1600 00A48093h 0FFFFFFh 2000 00A50093h 0FFFFFFh 2600 OOA5C093h 0FFFFFFh 3200 00A68093h 0FFFFFFh } } XC2V${ TYPE = FPGA IRLEN = 6 ALG = 1 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 } DEVICES{ 40 01008093h 0FFFFFFFh 80 01010093h 0FFFFFFFh 250 01018093h 0FFFFFFFh 500 01020093h 0FFFFFFFh 1000 01028093h 0FFFFFFFh 1500 01030093h 0FFFFFFFh 2000 01038093h 0FFFFFFFh 3000 01040093h 0FFFFFFFh 4000 01050093h 0FFFFFFFh 6000 01060093h 0FFFFFFFh 8000 01070093h 0FFFFFFFh } } XC2VP${ TYPE = FPGA IRLEN = 14 ALG = 2 COMMANDS{ CFG_OUT 00003FC4h ;---11111111000100 IDCODE 00003FC9h ;---11111111001001 CFG_IN 00003FC5h ;---11111111000101 JSTART 00003FCCh ;---11111111001100 BYPASS 00003FFFh ;---11111111111111 } DEVICES{ 30 0127e093h 0FFFFFFFh 40 01292093h 0FFFFFFFh 50 0129e093h 0FFFFFFFh 70 012ba093h 0FFFFFFFh 100 012d6093h 0FFFFFFFh } } XC4VFX${ TYPE = FPGA IRLEN = 10 ALG = 2 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 } DEVICES{ 12 01E58093h 0FFFFFFFh 20 01E64093h 0FFFFFFFh 60 01EB4093h 0FFFFFFFh } } XC4VLX${ TYPE = FPGA IRLEN = 10 ALG = 2 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 } DEVICES{ 15 01658093h 0FFFFFFFh 25 0167C093h 0FFFFFFFh 40 016A4093h 0FFFFFFFh 60 016B4093h 0FFFFFFFh 80 016D8093h 0FFFFFFFh 100 01700093h 0FFFFFFFh 160 01718093h 0FFFFFFFh 200 01734093h 0FFFFFFFh } } XC4VSX${ TYPE = FPGA IRLEN = 10 ALG = 2 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 } DEVICES{ 25 02068093h 0FFFFFFFh 35 02088093h 0FFFFFFFh 55 020b0093h 0FFFFFFFh } } XC5VFX$T{ TYPE = FPGA IRLEN = 10 ALG = 4 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 JPROGRAM 000003CBh ;---001111001011 } DEVICES{ 30 03276093h 0FFFFFFFh 70 032c6093h 0FFFFFFFh 100 032d8093h 0FFFFFFFh 130 03300093h 0FFFFFFFh 200 03334093 0FFFFFFFh } } XC5VLX$T{ TYPE = FPGA IRLEN = 10 ALG = 4 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 JPROGRAM 000003CBh ;---001111001011 } DEVICES{ 20 02a56093h 0FFFFFFFh 30 02a5e093h 0FFFFFFFh 50 02a96093h 0FFFFFFFh 85 02aae093h 0FFFFFFFh 110 02ad6093h 0FFFFFFFh 155 02aec093h 0FFFFFFFh 220 02b0c093h 0FFFFFFFh 330 02b05c93h 0FFFFFFFh } } XC5VSX$T{ TYPE = FPGA IRLEN = 10 ALG = 4 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 JPROGRAM 000003CBh ;---001111001011 } DEVICES{ 35 02e72093h 0FFFFFFFh 50 02e9a093h 0FFFFFFFh 95 02ece093h 0FFFFFFFh 240 02f3e093h 0FFFFFFFh } } XC5VTX$T{ TYPE = FPGA IRLEN = 10 ALG = 4 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 JPROGRAM 000003CBh ;---001111001011 } DEVICES{ 150 04502093h 0FFFFFFFh 240 0453e093h 0FFFFFFFh } } XC5VLX${ TYPE = FPGA IRLEN = 10 ALG = 4 COMMANDS{ CFG_OUT 000003c4h ;---1111000100 IDCODE 000003C9h ;---1111001001 CFG_IN 000003C5h ;---1111000101 JSTART 000003CCh ;---1111001100 BYPASS 000003FFh ;---1111111111 JPROGRAM 000003CBh ;---001111001011 } DEVICES{ 30 0286e093h 0FFFFFFFh 50 02896093h 0FFFFFFFh 85 028ae093h 0FFFFFFFh 110 028d6093h 0FFFFFFFh 155 028ec093h 0FFFFFFFh 220 0290c093h 0FFFFFFFh 330 0295c093h 0FFFFFFFh } } XC6VCX$T{ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---0000000100 IDCODE 00000009h ;---0000001001 CFG_IN 00000005h ;---0000000101 JSTART 0000000Ch ;---0000001100 BYPASS 0000000Fh ;---0000011111 JSHUTDOWN 0000000Dh ;---0000001101 JPROGRAM 0000000Bh ;---0000001011 } DEVICES{ 75 042c4093h 0FFFFFFFh 130 042ca093h 0FFFFFFFh 195 042cc093h 0FFFFFFFh 240 042d0093h 0FFFFFFFh } } XC6VLX$T{ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---0000000100 IDCODE 00000009h ;---0000001001 CFG_IN 00000005h ;---0000000101 JSTART 0000000Ch ;---0000001100 BYPASS 0000000Fh ;---0000011111 JSHUTDOWN 0000000Dh ;---0000001101 JPROGRAM 0000000Bh ;---0000001011 } DEVICES{ 75 04240093h 0FFFFFFFh 130 0424a093h 0FFFFFFFh 195 0424c093h 0FFFFFFFh 240 04250093h 0FFFFFFFh 365 04252093h 0FFFFFFFh 550 04256093h 0FFFFFFFh } } XC6VLX760T{ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---0000000100 IDCODE 00000009h ;---0000001001 CFG_IN 00000005h ;---0000000101 JSTART 0000000Ch ;---0000001100 BYPASS 0000000Fh ;---0000011111 JSHUTDOWN 0000000Dh ;---0000001101 JPROGRAM 0000000Bh ;---0000001011 } DEVICES{ 760 0423a093h 0FFFFFFFh } } XC6VSX$T{ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---0000000100 IDCODE 00000009h ;---0000001001 CFG_IN 00000005h ;---0000000101 JSTART 0000000Ch ;---0000001100 BYPASS 0000000Fh ;---0000011111 JSHUTDOWN 0000000Dh ;---0000001101 JPROGRAM 0000000Bh ;---0000001011 } DEVICES{ 315 04286093h 0FFFFFFFh 475 04288093h 0FFFFFFFh } } XC2S$E{ TYPE = FPGA IRLEN = 5 ALG = 1 COMMANDS{ CFG_OUT 00000004h ;---00100 IDCODE 00000009h ;---01001 CFG_IN 00000005h ;---00101 JSTART 0000000Ch ;---01100 BYPASS 0000001Fh ;---11111 } DEVICES{ 50 00A10093h 0FFFFFFFh 100 00A14093h 0FFFFFFFh 150 00A18093h 0FFFFFFFh 200 00A1C093h 0FFFFFFFh 300 00A20093h 0FFFFFFFh 400 00A28093h 0FFFFFFFh 600 00A20093h 0FFFFFFFh } } XC2S${ TYPE = FPGA IRLEN = 5 ALG = 1 COMMANDS{ CFG_OUT 00000004h ;---00100 IDCODE 00000009h ;---01001 CFG_IN 00000005h ;---00101 JSTART 0000000Ch ;---01100 BYPASS 0000001Fh ;---11111 } DEVICES{ 15 00608093h 0FFFFFFFh 30 0060C093h 0FFFFFFFh 50 00610093h 0FFFFFFFh 100 00614093h 0FFFFFFFh 150 00618093h 0FFFFFFFh 200 0061C093h 0FFFFFFFh } } XC3SD$A{ TYPE = FPGA IRLEN = 6 ALG = 3 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 1800 06840093h 0FFFFFFFh 3400 0684e093h 0FFFFFFFh } } XC3S$AN{ TYPE = FPGA IRLEN = 6 ALG = 3 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 50 02610093h 0FFFFFFFh 200 02618093h 0FFFFFFFh 400 02620093h 0FFFFFFFh 700 02628093h 0FFFFFFFh 1400 02630093h 0FFFFFFFh } } XC3S$A{ TYPE = FPGA IRLEN = 6 ALG = 3 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 50 02210093h 0FFFFFFFh 200 02218093h 0FFFFFFFh 400 02220093h 0FFFFFFFh 700 02228093h 0FFFFFFFh 1400 02230093h 0FFFFFFFh } } XC3S$E{ TYPE = FPGA IRLEN = 6 ALG = 3 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 100 01C10093h 0FFFFFFFh 250 01c1a093h 0FFFFFFFh 500 01C22093h 0FFFFFFFh 1200 01c2e093h 0FFFFFFFh 1600 01c3a093h 0FFFFFFFh } } XC3S${ TYPE = FPGA IRLEN = 6 ALG = 2 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 50 0140D093h 0FFFFFFFh 200 01414093h 0FFFFFFFh 400 0141C093h 0FFFFFFFh 1000 01428093h 0FFFFFFFh 1500 01434093h 0FFFFFFFh 2000 01440093h 0FFFFFFFh } } XC6SLX${ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 4 04000093h 0FFFFFFFh 16 04002093h 0FFFFFFFh 25 04004093h 0FFFFFFFh 45 04008093h 0FFFFFFFh 150 0401D093h 0FFFFFFFh } } XC7A$T{ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 15 0362e093h 0FFFFFFFh 35 0362d093h 0FFFFFFFh 100 03631093h 0FFFFFFFh 200 03636093h 0FFFFFFFh } } XC7K$T{ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 70 03647093h 0FFFFFFFh 160 0364C093h 0FFFFFFFh 325 03651093h 0FFFFFFFh 355 03747093h 0FFFFFFFh 410 03656093h 0FFFFFFFh 420 03752093h 0FFFFFFFh 480 03751093h 0FFFFFFFh } } XC7VX$T{ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 330 03667093h 0FFFFFFFh 415 03682093h 0FFFFFFFh 485 03687093h 0FFFFFFFh 550 03692093h 0FFFFFFFh 690 03691093h 0FFFFFFFh 980 03696093h 0FFFFFFFh } } XC7Z${ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 010 03722093h 0FFFFFFFh 015 0373B093h 0FFFFFFFh 020 03727093h 0FFFFFFFh 030 0372C093h 0FFFFFFFh 045 03731093h 0FFFFFFFh 100 03736093h 0FFFFFFFh } } ;----------- CPLD devices ----------- XC95${ TYPE = CPLD IRLEN = 8 ALG = 1 COMMANDS{ } DEVICES{ 36 29502093h 0FFFFFFFh 72 29504093h 0FFFFFFFh 108 29506093h 0FFFFFFFh 144 29508093h 0FFFFFFFh 216 29509093h 0FFFFFFFh 288 29516093h 0FFFFFFFh } } XC95$XL{ TYPE = CPLD IRLEN = 8 ALG = 1 COMMANDS{ } DEVICES{ 36 09602093h 0FFFFFFFh 72 09604093h 0FFFFFFFh 144 09608093h 0FFFFFFFh 288 09616093h 0FFFFFFFh } } XC95$XV{ TYPE = CPLD IRLEN = 8 ALG = 1 COMMANDS{ } DEVICES{ 36 09702093h 0FFFFFFFh 72 09704093h 0FFFFFFFh 144 09708093h 0FFFFFFFh 288 09716093h 0FFFFFFFh } } XCR3$XL{ TYPE = CPLD IRLEN = 5 ALG = 1 COMMANDS{ } DEVICES{ 32 0480802Bh 0FFF8FFFh 32 04808093h 0FFF8FFFh 64 0484802Bh 0FFF8FFFh 64 04848093h 0FFF8FFFh 128 0488802Bh 0FFF8FFFh 128 04888093h 0FFF8FFFh 256 0494802Bh 0FFF8FFFh 256 04948093h 0FFF8FFFh 384 0495802Bh 0FFF8FFFh 384 04958093h 0FFF8FFFh 512 0497802Bh 0FFF8FFFh 512 04978093h 0FFF8FFFh } } XC2C$A{ TYPE = CPLD IRLEN = 8 ALG = 1 COMMANDS{ BYPASS 000000FFh ;---11111111 IDCODE 00000001h ;---00000001 ISC_ENABLE 000000E8h ;---11101000 ISC_DISABLE 000000C0h ;---11000000 ISC_ERASE 000000EDh ;---11101101 ISC_INIT 000000F0h ;---11110000 ISC_READ 000000EEh ;---11101110 ISC_PROGRAM 000000EAh ;---11101010 } DEVICES{ 32 06E18093h 0FFF8FFFh 64 06E5e093h 0FFF8FFFh } } XC2C${ TYPE = CPLD IRLEN = 8 ALG = 1 COMMANDS{ BYPASS 000000FFh ;---11111111 IDCODE 00000001h ;---00000001 ISC_ENABLE 000000E8h ;---11101000 ISC_DISABLE 000000C0h ;---11000000 ISC_ERASE 000000EDh ;---11101101 ISC_INIT 000000F0h ;---11110000 ISC_READ 000000EEh ;---11101110 ISC_PROGRAM 000000EAh ;---11101010 } DEVICES{ 128 06D88093h 0FFF8FFFh 256 06D48093h 0FFF8FFFh 32 06C18093h 0FFF8FFFh 384 06D58093h 0FFF8FFFh 512 06D78093h 0FFF8FFFh 64 06c5e093h 0FFF8FFFh ;0904C093h 0FFFFFFFh } } ;----------- PROM devices ----------- XCF$S{ TYPE = PROM IRLEN = 8 ALG = 1 COMMANDS{ ISPEN 000000E8h ;---11101000 FPGM 000000EAh ;---11101010 FADDR 000000EBh ;---11101011 FVFY0 000000EFh ;---11101111 FVFY1 000000F8h ;---11111000 FVFY3 000000E2h ;---11100010 FVFY6 000000E6h ;---11100110 FERASE 000000ECh ;---11101100 SERASE 0000000Ah ;---00001010 FDATA0 000000EDh ;---11101101 FDATA3 000000F3h ;---11110011 FBLANK0 000000E5h ;---11100101 FBLANK3 000000E1h ;---11100001 FBLANK6 000000E4h ;---11100100 CONFIG 000000EEh ;---11101110 BYPASS 000000FFh ;---11111111 IDCODE 000000FEh ;---11111110 NORMRST 000000F0h ;---11110000 } DEVICES{ 01 05044093h 0FFFFFFFh 02 05045093h 0FFFFFFFh 04 05046093h 0FFFFFFFh } } XCF$P{ TYPE = PROM IRLEN = 16 ALG = 2 COMMANDS{ ISC_ERASE 000000ECh ;---0000000011101100 ISC_PROGRAM 000000EAh ;---0000000011101010 ISC_DATA_SHIFT 000000EDh ;---0000000011101101 ISC_ADDRESS_SHIFT 000000EBh ;---0000000011101011 XSC_UNLOCK 0000AA55h ;---1010101001010101 XSC_DATA_BTC 000000F2h ;---0000000011110010 XSC_DATA_SUCR 0000000Eh ;---0000000000001110 XSC_DATA_CCB 0000000Ch ;---0000000000001100 XSC_DATA_DONE 00000009h ;---0000000000001001 ISPEN 000000E8h ;---0000000011101000 NORMRST 000000F0h ;---0000000011110000 IDCODE 000000FEh ;---0000000011111110 BYPASS 0000FFFFh ;---1111111111111111 } DEVICES{ 08 05057093h 0FFFFFFFh 16 05058093h 0FFFFFFFh 32 05059093h 0FFFFFFFh } } XC18V${ TYPE = PROM IRLEN = 8 ALG = 1 COMMANDS{ } DEVICES{ 01 05024093h 0FFEFFFFh 02 05025093h 0FFEFFFFh 04 05026093h 0FFEFFFFh 512 05026093h 0FFEFFFFh } } XCCACE { TYPE = MISC IRLEN = 8 ALG = 1 COMMANDS{ } DEVICES{ 144 0a01093h 0FFFFFFFh } } ;---------- Xilinx ARM DAP ---------- ARM_DAP { TYPE = MISC IRLEN = 4 ALG = 1 COMMANDS{ } DEVICES{ ZYNQ7000 0BA00477h 0FFFFFFFh } } ;----------- unknown devices ----------- ;--- this segment must not be deleted ;--------------------------------------- UNKNOWN{ TYPE = UNKNOWN IRLEN = 0 ALG = 0 COMMANDS{ } DEVICES{ } } } UNKNOWN{ FAMILY{ UNKNOWN 00000000h 00000000h } UNKNOWN{ TYPE = UNKNOWN IRLEN = 0 ALG = 0 COMMANDS{ } DEVICES{ } } }