---------------------------------------------------------------------------------- -- Company: Digilent inc. 2011 -- Engineer: Michelle Yu -- -- Create Date: 14:35:23 08/30/2011 -- Module Name: EppPmod - Behavioral -- Project Name: PmodSF -- Target Devices: Nexys3 -- Tool versions: Xilinx ISE design suite 13.2 -- Description: -- This project uses the Epp component and the PmodSF component to demonstrate a basic Read/Write/Erase -- for the PmodSF -- Revision: -- Revision 0.01 - File Created ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity EppPmod is Port ( clk : in STD_LOGIC; EppAstb : in STD_LOGIC; EppDstb : in STD_LOGIC; UsbFlag : in STD_LOGIC; EppWait : out STD_LOGIC; EppDb : inout STD_LOGIC_VECTOR (7 downto 0); JA : inout STD_LOGIC_vector (7 downto 4)); end EppPmod; architecture Behavioral of EppPmod is component clkdiv is Port ( clk : in STD_LOGIC; clk100K : inout STD_LOGIC); end component; component EPP is Port ( Clk : in std_logic; EppAstb : in std_logic; EppDstb : in std_logic; EppWrite : in std_logic; EppWait : out std_logic; EppDB : inout std_logic_vector(7 downto 0); Address : out std_logic_vector(7 downto 0); DataOut : out std_logic_vector(7 downto 0); Read : out std_logic; Write : out std_logic; DataIn : in std_logic_vector(7 downto 0); DataRdy : in std_logic); end component ; component PModSF is Port ( Clk : in std_logic; Address : in std_logic_vector(7 downto 0); DataIn : in std_logic_vector(7 downto 0); DataOut : out std_logic_vector(7 downto 0); Read : in std_logic; Write : in std_logic; DataRdy : out std_logic; P1 : out std_logic; P2 : out std_logic; P3 : in std_logic; P4 : out std_logic); end component ; signal addr, dout, din: std_logic_vector(7 downto 0); signal R, W, rdy, divclk: std_logic; begin C0: clkdiv PORT MAP ( clk => clk, clk100K =>divclk); C1: EPP PORT MAP(Clk=>divclk, EppDB=>EppDB, EppAstb=>EppAstb, EppDstb=>EppDstb, EppWrite=>UsbFlag, EppWait=>EppWait, Address=>addr, DataOut => dout, Read=>R, Write=>W, DataIn=>din, DataRdy=>rdy ); C2: PModSF PORT MAP(Clk=>divclk, Address=> addr, DataIn=>dout, DataOut=>din, Read=>R, Write=>W, DataRdy=>rdy, P1=>JA(4), P2=>JA(5),P3=>JA(6),P4=>JA(7)); end Behavioral;