# ucf file
# This file is a general .ucf for Basys2 rev C board
# To use it in a project:
# - remove or comment the lines corresponding to unused pins
# - rename the used signals according to the project

# clock pin for Basys2 Board
NET "mclk" LOC = "B8"; # Bank = 0, Signal name = MCLK
#NET "uclk" LOC = "M6"; # Bank = 2, Signal name = UCLK
#NET "mclk" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "uclk" CLOCK_DEDICATED_ROUTE = FALSE;


# Loop Back only tested signals
NET "PIO<72>" LOC = "B2"; # | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA1
NET "PIO<73>" LOC = "A3"; # | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA2
NET "PIO<74>" LOC = "J3"; # | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA3
NET "PIO<75>" LOC = "B5"; # | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA4
################################################################################################


module clkdiv (input wire mclk , output wire clk25);

	reg [0:0] q; 
	initial q = 0;
	always @(posedge mclk)
	  begin
	    q <= q + 1;
	  end
  //assign clk190 = q[17]; // 190 Hz
	assign clk25 = q[0];   // 25 MHz
endmodule

############################################################################

module gates2_top(input wire mclk, output wire [75:72] PIO);

    wire clk25;	
	reg sync, din;
    assign PIO[72] = sync;
	assign PIO[73] = din;
    assign PIO[75] = clk25;
  //assign PIO[75] = mclk;
	assign PIO[74] = 0;
		
    clkdiv u0 (.mclk(mclk), .clk25(clk25));
    reg [5:0] i; reg first, second, done;
    initial i = 0;
    initial first = 1;
	initial second = 0;
    initial sync = 1;  
	initial done = 0;
		
	reg [31:0] command1;
	reg [31:0] command2; 
	//first command1 to use internal voltage
	initial command1 = 32'b00001000000000000000000000000001;
		
	//in the second command2 first 2 bits: 11
	//next 4 bits: 1111 - to use all 8 outputs
	//next 12 bit are '1' - to produce full voltage. AD5628 uses 12 bits to define value voltage from the max voltage.
  //initial command2 = 32'b00000011111111111111111100000000; // max voltage
  //initial command2 = 32'b00000011111101111111111100000000; // half of max voltage
	initial command2 = 32'b00000011111100111111111100000000; // fourth of max voltage
	
   always @ (posedge clk25)
	begin
		if (done == 0) 
		begin
			i <= i + 1;
			if (sync == 1 & i == 2)
				begin
					sync <= 0;
					i <= 1;	
				    if(first == 1)
				  	din <=  command1[31];
				    else if(second == 1)
				  	din <=  command2[31];
				end 
			else if(sync == 0)
				begin
				    if(i < 32)
					begin
						if(first == 1)
							din <=  command1[31 - i];
						else if(second == 1)
							din <=  command2[31 - i];
						end
					else if(i == 32)
						begin
							sync <= 1;				
							i <= 0;
							if(first == 1)
								begin
									first <= 0;
									second <= 1;
								end
							else if(second == 1)
								done <= 1;
						end
				end	
		end
	end
 
endmodule