# ucf file # This file is a general .ucf for Basys2 rev C board # To use it in a project: # - remove or comment the lines corresponding to unused pins # - rename the used signals according to the project # clock pin for Basys2 Board NET "mclk" LOC = "B8"; # Bank = 0, Signal name = MCLK #NET "uclk" LOC = "M6"; # Bank = 2, Signal name = UCLK #NET "mclk" CLOCK_DEDICATED_ROUTE = FALSE; #NET "uclk" CLOCK_DEDICATED_ROUTE = FALSE; # Loop Back only tested signals NET "PIO<72>" LOC = "B2"; # | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = JA1 NET "PIO<73>" LOC = "A3"; # | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = JA2 NET "PIO<74>" LOC = "J3"; # | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = JA3 NET "PIO<75>" LOC = "B5"; # | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = JA4 ################################################################################################ module gates2_top(input wire mclk, output wire [75:72] PIO); wire clk25, sync, din; assign PIO[72] = sync; assign PIO[73] = din; assign PIO[75] = clk25; //assign PIO[75] = mclk; assign PIO[74] = 0; clkdiv u1 (.mclk(mclk), .clk25(clk25)); wire [5:0] count; gates2 u5 (.clk(clk25), .sync(sync), .q(din), .i(count)); endmodule ############################################################################ module clkdiv (input wire mclk , output wire clk25); reg [0:0] q; initial q = 0; always @(posedge mclk) begin q <= q + 1; end //assign clk190 = q[17]; // 190 Hz assign clk25 = q[0]; // 25 MHz endmodule ############################################################################ module gates2 (input wire clk, output reg sync, output reg q, output reg [5:0] i); //integer i; //reg [5:0] i; initial sync = 1; initial i = 0; initial q = 0; always @ (posedge clk) begin i <= i + 1; if (i == 2) sync <= 0; if(i >= 3 & i <= 5) //first 4 bits - don`t care q <= 0; else if(i == 6)//bits 4-7 - mode of operation q <= 1; else if(i == 7) //bits 4-7 - mode of operation q <= 0; else if(i >= 8 & i <= 9) //bits 4-7 - mode of operation q <= 1; else if(i >= 10 & i <= 13) //4 bits 8-11 - pins with the voltage q <= 1; //all `1` - voltage on all 8 pins else if(i >= 14 & i <= 25) //level of voltage q <= 1; //all `1` - max voltage else if(i >= 26 & i <= 32) q <= 0; else if(i == 33) q <= 1; else if(i == 34) begin q <= 0; sync <= 1; i <= 0; end //i <= i + 1; end endmodule ######################################