Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.6 (WebPack) - P.68d Target Family: Zynq
OS Platform: NT64 Target Device: xc7z010
Project ID (random number) 98caef968e06475fbe4e90e49e6cd916.5073469E5DEE4518A0DC08CF12A8A101.1 Target Package: clg400
Registration ID 176233316_206049016_0_830 Target Speed: -2
Date Generated 2013-09-27T16:54:23 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-4670K CPU @ 3.40GHz CPU Speed 2993 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 12-bit adder=2
Comparators=12
  • 12-bit comparator greater=8
  • 12-bit comparator lessequal=4
Counters=5
  • 12-bit up counter=2
  • 12-bit updown counter=2
  • 25-bit up counter=1
Multiplexers=3
  • 5-bit 2-to-1 multiplexer=3
Registers=22
  • Flip-Flops=22
MiscellaneousStatistics
  • AGG_BONDED_IO=19
  • AGG_IO=19
  • AGG_LOCED_IO=19
  • AGG_SLICE=62
  • NUM_BONDED_IOB33=19
  • NUM_BSFULL=93
  • NUM_BSLUTONLY=96
  • NUM_BSREGONLY=2
  • NUM_BSUSED=191
  • NUM_BUFG=2
  • NUM_LOCED_IOB33=19
  • NUM_LOGIC_O5ANDO6=29
  • NUM_LOGIC_O5ONLY=43
  • NUM_LOGIC_O6ONLY=114
  • NUM_LUT_RT_DRIVES_CARRY4=3
  • NUM_LUT_RT_EXO6=3
  • NUM_LUT_RT_O5=2
  • NUM_LUT_RT_O6=43
  • NUM_MMCME2_ADV=1
  • NUM_SLICEL=62
  • NUM_SLICE_CARRY4=27
  • NUM_SLICE_CONTROLSET=6
  • NUM_SLICE_CYINIT=270
  • NUM_SLICE_FF=95
  • NUM_SLICE_UNUSEDCTRL=22
  • NUM_UNUSABLE_FF_BELS=25
NetStatistics
  • NumNets_Active=217
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BENTQUAD=40
  • NumNodesOfType_Active_BOUNCEACROSS=46
  • NumNodesOfType_Active_BOUNCEIN=39
  • NumNodesOfType_Active_BUFGROUT=2
  • NumNodesOfType_Active_BUFINP2OUT=3
  • NumNodesOfType_Active_CLKPIN=44
  • NumNodesOfType_Active_DOUBLE=330
  • NumNodesOfType_Active_GENERIC=4
  • NumNodesOfType_Active_GLOBAL=43
  • NumNodesOfType_Active_HQUAD=20
  • NumNodesOfType_Active_INPUT=60
  • NumNodesOfType_Active_IOBIN2OUT=19
  • NumNodesOfType_Active_IOBOUTPUT=19
  • NumNodesOfType_Active_LUTINPUT=644
  • NumNodesOfType_Active_OUTBOUND=183
  • NumNodesOfType_Active_OUTPUT=210
  • NumNodesOfType_Active_PADINPUT=18
  • NumNodesOfType_Active_PADOUTPUT=1
  • NumNodesOfType_Active_PINBOUNCE=115
  • NumNodesOfType_Active_PINFEED=746
  • NumNodesOfType_Active_SINGLE=462
  • NumNodesOfType_Active_VLONG12=3
  • NumNodesOfType_Active_VQUAD=46
  • NumNodesOfType_Vcc_HVCCGNDOUT=16
  • NumNodesOfType_Vcc_INPUT=1
  • NumNodesOfType_Vcc_LUTINPUT=74
  • NumNodesOfType_Vcc_PINFEED=75
SiteStatistics
  • BUFG-BUFGCTRL=2
  • IOB33-IOB33M=9
  • IOB33-IOB33S=9
  • SLICEL-SLICEM=15
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=27
  • FF_INIT=1
  • HARD0=3
  • HARD1=4
  • IOB33=19
  • IOB33_INBUF_EN=1
  • IOB33_OUTBUF=18
  • LUT5=74
  • LUT6=189
  • MMCME2_ADV=1
  • MMCME2_ADV_MMCME2_ADV=1
  • PAD=19
  • REG_INIT=94
  • SLICEL=62
 
Configuration Data
FF_INIT
  • CK=[CK:1] [CK_INV:0]
  • FFINIT=[INIT0:1]
  • FFSR=[SRLOW:1]
  • SYNC_ATTR=[ASYNC:1]
IOB33_INBUF_EN
  • IBUF_LOW_PWR=[TRUE:1]
MMCME2_ADV
  • CLKINSEL=[CLKINSEL:1] [CLKINSEL_INV:0]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • PWRDWN=[PWRDWN_INV:0] [PWRDWN:1]
  • RST=[RST:1] [RST_INV:0]
MMCME2_ADV_MMCME2_ADV
  • BANDWIDTH=[OPTIMIZED:1]
  • CLKBURST_ENABLE=[FALSE:1]
  • CLKBURST_REPEAT=[FALSE:1]
  • CLKFBIN_EDGE=[FALSE:1]
  • CLKFBIN_NOCOUNT=[TRUE:1]
  • CLKFBOUT_EDGE=[FALSE:1]
  • CLKFBOUT_EN=[TRUE:1]
  • CLKFBOUT_FRAC_EN=[FALSE:1]
  • CLKFBOUT_FRAC_WF_FALL=[FALSE:1]
  • CLKFBOUT_FRAC_WF_RISE=[FALSE:1]
  • CLKFBOUT_NOCOUNT=[TRUE:1]
  • CLKFBOUT_USE_FINE_PS=[FALSE:1]
  • CLKINSEL=[CLKINSEL:1] [CLKINSEL_INV:0]
  • CLKOUT0_EDGE=[FALSE:1]
  • CLKOUT0_EN=[FALSE:1]
  • CLKOUT0_FRAC_EN=[FALSE:1]
  • CLKOUT0_FRAC_WF_FALL=[FALSE:1]
  • CLKOUT0_FRAC_WF_RISE=[FALSE:1]
  • CLKOUT0_NOCOUNT=[TRUE:1]
  • CLKOUT0_USE_FINE_PS=[FALSE:1]
  • CLKOUT1_EDGE=[FALSE:1]
  • CLKOUT1_EN=[FALSE:1]
  • CLKOUT1_NOCOUNT=[TRUE:1]
  • CLKOUT1_USE_FINE_PS=[FALSE:1]
  • CLKOUT2_EDGE=[FALSE:1]
  • CLKOUT2_EN=[FALSE:1]
  • CLKOUT2_NOCOUNT=[TRUE:1]
  • CLKOUT2_USE_FINE_PS=[FALSE:1]
  • CLKOUT3_EDGE=[FALSE:1]
  • CLKOUT3_EN=[FALSE:1]
  • CLKOUT3_NOCOUNT=[TRUE:1]
  • CLKOUT3_USE_FINE_PS=[FALSE:1]
  • CLKOUT4_CASCADE=[FALSE:1]
  • CLKOUT4_EDGE=[FALSE:1]
  • CLKOUT4_EN=[FALSE:1]
  • CLKOUT4_NOCOUNT=[TRUE:1]
  • CLKOUT4_USE_FINE_PS=[FALSE:1]
  • CLKOUT5_EDGE=[FALSE:1]
  • CLKOUT5_EN=[FALSE:1]
  • CLKOUT5_NOCOUNT=[TRUE:1]
  • CLKOUT5_USE_FINE_PS=[FALSE:1]
  • CLKOUT6_EDGE=[FALSE:1]
  • CLKOUT6_EN=[FALSE:1]
  • CLKOUT6_NOCOUNT=[TRUE:1]
  • CLKOUT6_USE_FINE_PS=[FALSE:1]
  • COMPENSATION=[ZHOLD:1]
  • DIRECT_PATH_CNTRL=[FALSE:1]
  • DIVCLK_EDGE=[FALSE:1]
  • DIVCLK_NOCOUNT=[TRUE:1]
  • EN_VCO_DIV1=[FALSE:1]
  • EN_VCO_DIV6=[FALSE:1]
  • GTS_WAIT=[FALSE:1]
  • HVLF_CNT_TEST_EN=[FALSE:1]
  • INTERP_TEST=[FALSE:1]
  • IN_DLY_EN=[TRUE:1]
  • LF_LOW_SEL=[FALSE:1]
  • MMCM_EN=[TRUE:1]
  • PERF0_USE_CLK=[FALSE:1]
  • PERF1_USE_CLK=[FALSE:1]
  • PERF2_USE_CLK=[FALSE:1]
  • PERF3_USE_CLK=[FALSE:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • PWRDWN=[PWRDWN_INV:0] [PWRDWN:1]
  • RST=[RST:1] [RST_INV:0]
  • SEL_HV_NMOS=[FALSE:1]
  • SEL_LV_NMOS=[FALSE:1]
  • SEL_SLIPD=[FALSE:1]
  • SS_EN=[FALSE:1]
  • SS_MODE=[CENTER_HIGH:1]
  • STARTUP_WAIT=[FALSE:1]
  • SUP_SEL_AREG=[FALSE:1]
  • SUP_SEL_DREG=[FALSE:1]
  • TMUX_MUX_SEL=[00:1]
  • VLF_HIGH_DIS_B=[TRUE:1]
  • VLF_HIGH_PWDN_B=[TRUE:1]
REG_INIT
  • CK=[CK:94] [CK_INV:0]
  • FFINIT=[INIT0:89] [INIT1:5]
  • FFSR=[SRLOW:94]
  • LATCH_OR_FF=[FF:94]
  • SYNC_ATTR=[ASYNC:57] [SYNC:37]
SLICEL
  • CLK=[CLK:40] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
CARRY4
  • CIN=18
  • CO1=4
  • CO3=18
  • CYINIT=9
  • DI0=26
  • DI1=26
  • DI2=22
  • DI3=18
  • O0=19
  • O1=18
  • O2=18
  • O3=18
  • S0=27
  • S1=26
  • S2=22
  • S3=22
FF_INIT
  • CK=1
  • D=1
  • Q=1
HARD0
  • 0=3
HARD1
  • 1=4
IOB33
  • I=1
  • O=18
  • PAD=19
IOB33_INBUF_EN
  • OUT=1
  • PAD=1
IOB33_OUTBUF
  • IN=18
  • OUT=18
LUT5
  • A1=2
  • A2=26
  • A3=26
  • A4=28
  • A5=26
  • O5=74
LUT6
  • A1=48
  • A2=81
  • A3=102
  • A4=171
  • A5=127
  • A6=185
  • O6=189
MMCME2_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKIN2=1
  • CLKINSEL=1
  • CLKOUT0=1
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DADDR5=1
  • DADDR6=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DWE=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • PWRDWN=1
  • RST=1
MMCME2_ADV_MMCME2_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKIN2=1
  • CLKINSEL=1
  • CLKOUT0=1
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DADDR5=1
  • DADDR6=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DWE=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • PWRDWN=1
  • RST=1
PAD
  • PAD=19
REG_INIT
  • CE=26
  • CK=94
  • D=94
  • Q=94
  • SR=37
SLICEL
  • A=11
  • A1=16
  • A2=24
  • A3=29
  • A4=47
  • A5=35
  • A6=48
  • AMUX=5
  • AQ=30
  • AX=8
  • B=19
  • B1=11
  • B2=25
  • B3=30
  • B4=47
  • B5=35
  • B6=50
  • BMUX=8
  • BQ=20
  • BX=6
  • C=14
  • C1=10
  • C2=16
  • C3=22
  • C4=38
  • C5=27
  • C6=42
  • CE=8
  • CIN=18
  • CLK=40
  • CMUX=3
  • COUT=18
  • CQ=23
  • CX=6
  • D=18
  • D1=13
  • D2=18
  • D3=21
  • D4=39
  • D5=30
  • D6=45
  • DMUX=3
  • DQ=21
  • DX=4
  • SR=10
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc7z010-clg400-2 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc7z010-clg400-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc7z010-clg400-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 5 4 0 0 0 0 0
bitgen 4 4 0 0 0 0 0
libgen 10 10 0 0 0 0 0
map 4 4 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 5 4 0 0 0 0 0
par 4 4 0 0 0 0 0
platgen 1 1 0 0 0 0 0
psf2Edward 1 1 0 0 0 0 0
trce 4 4 0 0 0 0 0
xdsgen 1 1 0 0 0 0 0
xps 3 3 0 0 0 0 0
xst 12 12 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/platform_studio/ps_c_ipw_define_axi4stream_bus_interface_settings.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-09-27T16:48:47
PROP_intWbtProjectID=5073469E5DEE4518A0DC08CF12A8A101 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Zynq
PROP_DevDevice=xc7z010 PROP_DevFamilyPMName=zynq
PROP_DevPackage=clg400 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-2 PROP_PreferredLanguage=VHDL
FILE_COREGEN=1 FILE_UCF=1
FILE_VHDL=1
 
Core Statistics
Core Type=clk_wiz_v3_6
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=MANUAL feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=1 primtype_sel=MMCM_ADV
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=false use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=false
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=32 NGDBUILD_NUM_FDE=26 NGDBUILD_NUM_FDR=37
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=7 NGDBUILD_NUM_LUT1=46
NGDBUILD_NUM_LUT2=30 NGDBUILD_NUM_LUT3=8 NGDBUILD_NUM_LUT4=67 NGDBUILD_NUM_LUT5=11
NGDBUILD_NUM_LUT6=48 NGDBUILD_NUM_MMCME2_ADV=1 NGDBUILD_NUM_MUXCY=92 NGDBUILD_NUM_OBUF=18
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=73
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=32 NGDBUILD_NUM_FDE=26 NGDBUILD_NUM_FDR=37
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=7 NGDBUILD_NUM_LUT1=46
NGDBUILD_NUM_LUT2=30 NGDBUILD_NUM_LUT3=8 NGDBUILD_NUM_LUT4=67 NGDBUILD_NUM_LUT5=11
NGDBUILD_NUM_LUT6=48 NGDBUILD_NUM_MMCME2_ADV=1 NGDBUILD_NUM_MUXCY=92 NGDBUILD_NUM_OBUF=18
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=73
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc7z010-2-clg400
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=32 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5