top Project Status
Project File: ZyBo_VGA.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc7z010-2clg400
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
2 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 95 35,200 1%  
    Number used as Flip Flops 95      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 189 17,600 1%  
    Number used as logic 186 17,600 1%  
        Number using O6 output only 114      
        Number using O5 output only 43      
        Number using O5 and O6 29      
        Number used as ROM 0      
    Number used as Memory 0 6,000 0%  
    Number used exclusively as route-thrus 3      
        Number with same-slice register load 0      
        Number with same-slice carry load 3      
        Number with other load 0      
Number of occupied Slices 62 4,400 1%  
Number of LUT Flip Flop pairs used 191      
    Number with an unused Flip Flop 96 191 50%  
    Number with an unused LUT 2 191 1%  
    Number of fully used LUT-FF pairs 93 191 48%  
    Number of unique control sets 6      
    Number of slice register sites lost
        to control set restrictions
25 35,200 1%  
Number of bonded IOBs 19 100 19%  
    Number of LOCed IOBs 19 19 100%  
Number of RAMB36E1/FIFO36E1s 0 60 0%  
Number of RAMB18E1/FIFO18E1s 0 120 0%  
Number of BUFG/BUFGCTRLs 2 32 6%  
    Number used as BUFGs 2      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 100 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 100 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 100 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 8 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 8 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 48 0%  
Number of BUFRs 0 8 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 80 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 2 0%  
Number of IN_FIFOs 0 8 0%  
Number of MMCME2_ADVs 1 2 50%  
Number of OUT_FIFOs 0 8 0%  
Number of PHASER_REFs 0 2 0%  
Number of PHY_CONTROLs 0 2 0%  
Number of PLLE2_ADVs 0 2 0%  
Number of PS7s 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.94      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Sep 27 16:52:21 2013000
Translation ReportCurrentFri Sep 27 16:52:48 2013000
Map ReportCurrentFri Sep 27 16:53:25 201301 Warning (1 new)4 Infos (4 new)
Place and Route ReportCurrentFri Sep 27 16:53:43 2013002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Sep 27 16:53:56 2013004 Infos (4 new)
Bitgen ReportCurrentFri Sep 27 16:54:22 201301 Warning (1 new)1 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateFri Sep 27 16:54:23 2013
WebTalk Log FileOut of DateFri Sep 27 16:54:27 2013

Date Generated: 09/09/2016 - 12:59:10