Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2013-09-27T16:48:47 |
PROP_intWbtProjectID=5073469E5DEE4518A0DC08CF12A8A101 |
PROP_intWbtProjectIteration=1 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_AutoTop=true |
PROP_DevFamily=Zynq |
PROP_DevDevice=xc7z010 |
PROP_DevFamilyPMName=zynq |
PROP_DevPackage=clg400 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=VHDL |
FILE_COREGEN=1 |
FILE_UCF=1 |
FILE_VHDL=1 |