library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use iEEE.NUMERIC_STD.ALL; entity TL_Counter is Port ( clk : in STD_LOGIC; RESULT : out STD_LOGIC_VECTOR (3 downto 0)); end TL_Counter; architecture Behavioral of TL_Counter is component clk_core is Port ( clk_in_125MHz : in STD_LOGIC; clk_out_5MHz : out STD_LOGIC); end component; component Counter is Port ( Cntr_in : in STD_LOGIC; Count : out STD_LOGIC_VECTOR(23 DOWNTO 0)); end component; signal s_clk : STD_LOGIC ; signal s_Cntr_in : STD_LOGIC ; signal s_Count : STD_LOGIC_VECTOR(23 downto 0) := X"000000" ; begin s_clk <= clk ; clk_5MHz : clk_core port map( clk_in_125MHz => s_clk, clk_out_5MHz => s_Cntr_in); cntr : Counter port map( Cntr_in => s_Cntr_in, Count => s_Count); RESULT <= s_Count(23 downto 20) ; end Behavioral;