[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'xillybus_ins/system_i/vivado_system_i/xillyvga_0/inst/xillyvga_core_ins' of type 'xillybus_ins/system_i/vivado_system_i/xillyvga_0/inst/xillyvga_core_ins/xillyvga_core' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.
 [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'xillybus_ins/xillybus_core_ins' of type 'xillybus_ins/xillybus_core_ins/xillybus_core' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.
 [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
 [Designutils 20-1280] Could not find module 'vga_fifo'. The XDC file /home/tuan/VBox_shared/200MHz_Ubuntu/xillinux-eval-zybo-1.3c/vivado-essentials/vga_fifo/vga_fifo/vga_fifo.xdc will not be read for any cell of this module.
 [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_clocks vga_clk_ins/*]'. [/home/tuan/VBox_shared/200MHz_Ubuntu/xillinux-eval-zybo-1.3c/vivado-essentials/xillydemo.xdc:8]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
 [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-from [get_clocks vga_clk_ins/*]'. [/home/tuan/VBox_shared/200MHz_Ubuntu/xillinux-eval-zybo-1.3c/vivado-essentials/xillydemo.xdc:9]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
 [Common 17-55] 'set_property' expects at least one object. [/home/tuan/VBox_shared/200MHz_Ubuntu/xillinux-eval-zybo-1.3c/vivado-essentials/xillydemo.xdc:20]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
 [Designutils 20-1280] Could not find module 'vga_fifo'. The XDC file /home/tuan/VBox_shared/200MHz_Ubuntu/xillinux-eval-zybo-1.3c/vivado-essentials/vga_fifo/vga_fifo/vga_fifo_clocks.xdc will not be read for any cell of this module.
 [Project 1-486] Could not resolve non-primitive black box cell 'xillybus_core' instantiated as 'xillybus_ins/xillybus_core_ins' [/home/tuan/VBox_shared/200MHz_Ubuntu/xillinux-eval-zybo-1.3c/verilog/src/xillybus.v:341]
 [Project 1-486] Could not resolve non-primitive black box cell 'xillyvga_core' instantiated as 'xillybus_ins/system_i/vivado_system_i/xillyvga_0/inst/xillyvga_core_ins' [/home/tuan/VBox_shared/200MHz_Ubuntu/xillinux-eval-zybo-1.3c/vivado-essentials/vivado_system/ip/vivado_system_xillyvga_0_0/work/xillyvga.srcs/sources_1/imports/verilog/xillyvga.v:68]