`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 06/12/2016 01:43:07 PM
// Design Name: 
// Module Name: MainSource
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module MainSource(
input CLK100MHZ ,
input vp , 
input vn ,
output reg [15:0] OUT,
output reg [9:0] Xk_Index 

    );
 //ADC:    
 wire enable ; 
 wire ready ; 
 wire [15:0] data ; 
 wire [6:0] Address ;
  
 
 //FFT : 
 wire FFT_Ready_in ; 
 wire FFT_valid_out ; 
 wire Config_data ; 
 wire Config_valid ; 
 wire Config_ready ; 
 reg [15:0] FFT_input ;
 wire [63:0]FFT_data_out ;
 reg [63:0] Output ; 
 wire [9:0] Xk_index; 
 
   
// Multipliers and Adder
 wire[63:0] RE_OUT ; 
 wire[63:0] IM_OUT ;
 wire[63:0] Adder_out ;
 
 // FIFO of the adder 
  wire empty0 ;
  wire full0 ; 
  reg [0:0] rd_en0 ; 
  reg [0:0] wr_en0 ;
  reg [63:0] din0 ;
  wire[63:0] dout0 ; 

 // Square Root Parameters 
 wire SRoot_validin  ; 
 wire SRoot_validout ; 
 reg [63:0] SR_input ;
 wire[31:0] SR_output;  
  
  
 assign Address = 2'h03 ; 
 assign Config_valid = 1'b1 ;    
 assign Config_data = 1'b1 ;  //FORWARD FFT
 assign SR_valid_in = 1'b1 ;
 
//-------------------------------------------------------------------------------------------- 

always @(posedge(CLK100MHZ))
  begin 
   if(FFT_Ready_in)
     if(ready)
       FFT_input <= data ; 
  end    
   
 // ------------------------------------------------------------
   
 xadc_wiz_0 XADC (
   .di_in(),              // input wire [15 : 0] di_in
   .daddr_in(Address),        // input wire [6 : 0] daddr_in
   .den_in(enable),            // input wire den_in
   .dwe_in(),            // input wire dwe_in
   .drdy_out(ready),        // output wire drdy_out
   .do_out(data),            // output wire [15 : 0] do_out
   .dclk_in(CLK100MHZ),          // input wire dclk_in
   .vp_in(vp),              // input wire vp_in
   .vn_in(vn),              // input wire vn_in
   .channel_out(),  // output wire [4 : 0] channel_out
   .eoc_out(enable),          // output wire eoc_out
   .alarm_out(),      // output wire alarm_out
   .eos_out(),          // output wire eos_out
   .busy_out()        // output wire busy_out
 );   
 
 
 xfft_0 FFT1024 (
  .aclk(CLK100MHZ),                                              // input wire aclk
  .s_axis_config_tdata(Config_data),                // input wire [7 : 0] s_axis_config_tdata
  .s_axis_config_tvalid(Config_valid),              // input wire s_axis_config_tvalid
  .s_axis_config_tready(Config_ready),              // output wire s_axis_config_tready
  .s_axis_data_tdata(FFT_input),                    // input wire [31 : 0] s_axis_data_tdata
  .s_axis_data_tvalid(ready),                  // input wire s_axis_data_tvalid
  .s_axis_data_tready(FFT_Ready_in),                  // output wire s_axis_data_tready
  .s_axis_data_tlast(),                    // input wire s_axis_data_tlast
  .m_axis_data_tdata(FFT_data_out),                    // output wire [63 : 0] m_axis_data_tdata
  .m_axis_data_tuser(Xk_index),                    // output wire [15 : 0] m_axis_data_tuser
  .m_axis_data_tvalid(FFT_valid_out),                  // output wire m_axis_data_tvalid
  .m_axis_data_tlast(),                    // output wire m_axis_data_tlast
  .event_frame_started(),                // output wire event_frame_started
  .event_tlast_unexpected(),          // output wire event_tlast_unexpected
  .event_tlast_missing(),                // output wire event_tlast_missing
  .event_data_in_channel_halt()  // output wire event_data_in_channel_halt
);
 
 always @(posedge CLK100MHZ) 
   if(FFT_valid_out) 
      Output <= FFT_data_out ;
      
  always @(posedge(CLK100MHZ))
    Xk_Index <= Xk_index ;   
      
 mult_gen_0 RE_Sq (
   .CLK(CLK100MHZ),
   .A(Output[31:0]),  // input wire [31 : 0] A
   .B(Output[31:0]),  // input wire [31 : 0] B
   .P(RE_OUT)  // output wire [63 : 0] P
 );
 mult_gen_1 IM_Sq (
   .CLK(CLK100MHZ),        // input wire CLK
   .A(Output[63:32]),      // input wire [31 : 0] A
   .B(Output[63:32]),      // input wire [31 : 0] B
   .P(IM_OUT)             //  output wire [63 : 0] P
 );
 
 c_addsub_0 Adder (
   .A(RE_OUT),      // input wire [63 : 0] A
   .B(IM_OUT),      // input wire [63 : 0] B
   .CLK(CLK100MHZ),  // input wire CLK
   .S(Adder_out)      // output wire [63 : 0] S
 );
  
 fifo_generator_0 Adder_FIFO (
   .clk(CLK100MHZ),      // input wire clk
   .din(din0),      // input wire [63 : 0] din
   .wr_en(wr_en0),  // input wire wr_en
   .rd_en(rd_en0),  // input wire rd_en
   .dout(dout0),    // output wire [63 : 0] dout
   .full(full0),    // output wire full
   .empty(empty0)  // output wire empty
 );
 always @(posedge (CLK100MHZ))
  if(empty0) 
    wr_en0 = 1'b1 ;
    else wr_en0 = 1'b0 ;
    
 always @(posedge (CLK100MHZ))
      if(full0) 
        rd_en0 = 1'b1 ;  
        else rd_en0 = 1'b0 ;
 
 always @(posedge (CLK100MHZ))
   if(wr_en0)
     din0 <= Adder_out ; 
 
 assign SRoot_validin = rd_en0 ; 
     
 always @(posedge (CLK100MHZ))
   if(rd_en0)
     SR_input <= dout0 ; 
   
cordic_0 S_Root(
  .aclk(CLK100MHZ),                                        // input wire aclk
  .s_axis_cartesian_tvalid(SRoot_validin),  // input wire s_axis_cartesian_tvalid
  .s_axis_cartesian_tdata(SR_input),       // input wire [63 : 0] s_axis_cartesian_tdata
  .m_axis_dout_tvalid(SRoot_validout),            // output wire m_axis_dout_tvalid
  .m_axis_dout_tdata(SR_output)              // output wire [31 : 0] m_axis_dout_tdata
);         
 
 always @(posedge (CLK100MHZ))
   if(SRoot_validout)
      OUT <= SR_output ;     
 
// -------------------------------------------  

    
 
endmodule