PK ƫQ uart/PK 䩖Q uart/uart.cache/PK 䩖Q uart/uart.cache/ip/PK ϫQ uart/uart.cache/ip/2019.1/PK Q uart/uart.cache/wt/PK
ϫQ'i- - # uart/uart.cache/wt/gui_handlers.wdfversion:1
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f636c6f7365:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3130:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6578706c6f72656168656164766965775f73686f775f70657263656e74616765:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3131:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3134:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d696f636f6e666967747265657461626c6570616e656c5f6d696f5f636f6e6669675f747265655f7461626c65:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d616e6167655f7375707072657373696f6e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:35:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f706f7274735f77696e646f77:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f726567656e65726174655f6c61796f7574:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706c616e61686561647461625f726566726573685f6368616e6765645f6d6f64756c6573:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f70726f6772616d5f646576696365:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7273626170706c796175746f6d6174696f6e6261725f72756e5f626c6f636b5f6175746f6d6174696f6e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7369676e616c7472656570616e656c5f7369676e616c5f747265655f7461626c65:37:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c6465726d656e755f6164645f6d6f64756c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c646572766965775f6164645f6970:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c646572766965775f70696e6e696e67:31:00:00
eof:767550139
PK
ϫQ܌ , uart/uart.cache/wt/java_command_handlers.wdfversion:1
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637265617465626c6f636b64657369676e:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65727362626c6f636b:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:726567656e65726174657273626c61796f7574:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:35:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
eof:266105231
PK
@Q^3y y uart/uart.cache/wt/project.wpcversion:1
57656254616c6b5472616e736d697373696f6e417474656d70746564:1
6d6f64655f636f756e7465727c4755494d6f6465:1
eof:
PK
몖Q: uart/uart.cache/wt/synthesis.wdfversion:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303230636c673430302d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:746f70:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353273:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313032302e3533394d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3633302e3530304d42:00:00
eof:1132868214
PK
۪Q-d d ( uart/uart.cache/wt/synthesis_details.wdfversion:1
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
eof:2511430288
PK
ϫQTz ! uart/uart.cache/wt/webtalk_pa.xml
PK ZQ
uart/uart.hw/PK WQ uart/uart.hw/hw_1/PK
ZQy
uart/uart.hw/hw_1/hw.xml
PK NQ uart/uart.hw/hw_1/wave/PK
NQMLW W uart/uart.hw/uart.lpr
PK ƫQ uart/uart.ioplanning/PK ƫQ uart/uart.ioplanning/constrs_1/PK ©Q uart/uart.ip_user_files/PK 䩖Q uart/uart.runs/PK ϫQ uart/uart.runs/.jobs/PK
䩖QH$ % uart/uart.runs/.jobs/vrs_config_1.xml
PK
ʪQdl % uart/uart.runs/.jobs/vrs_config_2.xml
PK
TQ~E E % uart/uart.runs/.jobs/vrs_config_3.xml
PK
ϫQ[A A % uart/uart.runs/.jobs/vrs_config_4.xml
PK Q uart/uart.runs/impl_1/PK
ӫQK6 , uart/uart.runs/impl_1/.init_design.begin.rst
PK
Q * uart/uart.runs/impl_1/.init_design.end.rstPK
QK6 + uart/uart.runs/impl_1/.opt_design.begin.rst
PK
Q ) uart/uart.runs/impl_1/.opt_design.end.rstPK
QK6 - uart/uart.runs/impl_1/.place_design.begin.rst
PK
Q + uart/uart.runs/impl_1/.place_design.end.rstPK
QK6 - uart/uart.runs/impl_1/.route_design.begin.rst
PK
Q + uart/uart.runs/impl_1/.route_design.end.rstPK
ҫQ ' uart/uart.runs/impl_1/.vivado.begin.rst
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ϫQ 6 uart/uart.runs/impl_1/.Vivado_Implementation.queue.rstPK
QK6 0 uart/uart.runs/impl_1/.write_bitstream.begin.rst
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Q 0 uart/uart.runs/impl_1/.write_bitstream.error.rstPK Q uart/uart.runs/impl_1/.Xil/PK
Q& & ! uart/uart.runs/impl_1/gen_run.xml
Default settings for Implementation.
PK
ϫQJ( uart/uart.runs/impl_1/htr.txtREM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
REM
vivado -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
PK
QR2 $ uart/uart.runs/impl_1/init_design.pb
o
Command: %s
53* vivadotcl2>
*link_design -top top -part xc7z020clg400-12default:defaultZ4-113h px
g
#Design is defaulting to srcset: %s
437* planAhead2
sources_12default:defaultZ12-437h px
j
&Design is defaulting to constrset: %s
434* planAhead2
constrs_12default:defaultZ12-434h px
V
Loading part %s157*device2#
xc7z020clg400-12default:defaultZ21-403h px
f
-Analyzing %s Unisim elements for replacement
17*netlist2
122default:defaultZ29-17h px
j
2Unisim Transformation completed in %s CPU seconds
28*netlist2
02default:defaultZ29-28h px
x
Netlist was created with %s %s291*project2
Vivado2default:default2
2019.12default:defaultZ1-479h px
K
)Preparing netlist for logic optimization
349*projectZ1-570h px
Parsing XDC File [%s]
179*designutils2j
TC:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc2default:default8Z20-179h px
Finished Parsing XDC File [%s]
178*designutils2j
TC:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc2default:default8Z20-178h px
u
)Pushed %s inverter(s) to %s load pin(s).
98*opt2
02default:default2
02default:defaultZ31-138h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:002default:default2
781.8912default:default2
0.0002default:defaultZ17-268h px
~
!Unisim Transformation Summary:
%s111*project29
%No Unisim elements were transformed.
2default:defaultZ1-111h px
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28* vivadotcl2
72default:default2
02default:default2
02default:default2
02default:defaultZ4-41h px
]
%s completed successfully
29* vivadotcl2
link_design2default:defaultZ4-42h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2!
link_design: 2default:default2
00:00:172default:default2
00:00:192default:default2
785.9262default:default2
415.0622default:defaultZ17-268h px
End RecordPK
ΫQ) uart/uart.runs/impl_1/ISEWrap.js//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "" );
ISEBeginFile.WriteLine( "" );
ISEBeginFile.WriteLine( " " );
ISEBeginFile.WriteLine( " " );
ISEBeginFile.WriteLine( "" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
PK
ϫQ uart/uart.runs/impl_1/ISEWrap.sh#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
if [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "" >> $ISE_BEGINFILE
echo "" >> $ISE_BEGINFILE
echo " " >> $ISE_BEGINFILE
echo " " >> $ISE_BEGINFILE
echo "" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
PK
Q*, *, # uart/uart.runs/impl_1/opt_design.pb
O
Command: %s
53* vivadotcl2
opt_design2default:defaultZ4-113h px
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xc7z0202default:defaultZ17-347h px
0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xc7z0202default:defaultZ17-349h px
n
,Running DRC as a precondition to command %s
22* vivadotcl2
opt_design2default:defaultZ4-22h px
R
Starting %s Task
103*constraints2
DRC2default:defaultZ18-103h px
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px
U
DRC finished with %s
272*project2
0 Errors2default:defaultZ1-461h px
d
BPlease refer to the DRC report (report_drc) for more information.
274*projectZ1-462h px
%s
*constraints2o
[Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 803.875 ; gain = 17.9492default:defaulth px
g
Starting %s Task
103*constraints2,
Cache Timing Information2default:defaultZ18-103h px
E
%Done setting XDC timing constraints.
35*timingZ38-35h px
P
;Ending Cache Timing Information Task | Checksum: 2190fe924
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1333.379 ; gain = 529.5042default:defaulth px
a
Starting %s Task
103*constraints2&
Logic Optimization2default:defaultZ18-103h px
i
Phase %s%s
101*constraints2
1 2default:default2
Retarget2default:defaultZ18-101h px
u
)Pushed %s inverter(s) to %s load pin(s).
98*opt2
02default:default2
02default:defaultZ31-138h px
K
Retargeted %s cell(s).
49*opt2
02default:defaultZ31-49h px
<
'Phase 1 Retarget | Checksum: 2190fe924
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.160 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
.Phase %s created %s cells and removed %s cells267*opt2
Retarget2default:default2
02default:default2
02default:defaultZ31-389h px
u
Phase %s%s
101*constraints2
2 2default:default2(
Constant propagation2default:defaultZ18-101h px
u
)Pushed %s inverter(s) to %s load pin(s).
98*opt2
02default:default2
02default:defaultZ31-138h px
H
3Phase 2 Constant propagation | Checksum: 2190fe924
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.165 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
.Phase %s created %s cells and removed %s cells267*opt2(
Constant propagation2default:default2
02default:default2
02default:defaultZ31-389h px
f
Phase %s%s
101*constraints2
3 2default:default2
Sweep2default:defaultZ18-101h px
9
$Phase 3 Sweep | Checksum: 2608436f6
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.204 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
.Phase %s created %s cells and removed %s cells267*opt2
Sweep2default:default2
02default:default2
02default:defaultZ31-389h px
r
Phase %s%s
101*constraints2
4 2default:default2%
BUFG optimization2default:defaultZ18-101h px
E
0Phase 4 BUFG optimization | Checksum: 2608436f6
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.218 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
EPhase %s created %s cells of which %s are BUFGs and removed %s cells.395*opt2%
BUFG optimization2default:default2
02default:default2
02default:default2
02default:defaultZ31-662h px
|
Phase %s%s
101*constraints2
5 2default:default2/
Shift Register Optimization2default:defaultZ18-101h px
dSRL Remap converted %s SRLs to %s registers and converted %s registers of register chains to %s SRLs546*opt2
02default:default2
02default:default2
02default:default2
02default:defaultZ31-1064h px
O
:Phase 5 Shift Register Optimization | Checksum: 2608436f6
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.227 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
.Phase %s created %s cells and removed %s cells267*opt2/
Shift Register Optimization2default:default2
02default:default2
02default:defaultZ31-389h px
x
Phase %s%s
101*constraints2
6 2default:default2+
Post Processing Netlist2default:defaultZ18-101h px
K
6Phase 6 Post Processing Netlist | Checksum: 2608436f6
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.231 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
.Phase %s created %s cells and removed %s cells267*opt2+
Post Processing Netlist2default:default2
02default:default2
02default:defaultZ31-389h px
/
Opt_design Change Summary
*commonh px
/
=========================
*commonh px
*commonh px
*commonh px
z-------------------------------------------------------------------------------------------------------------------------
*commonh px
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
*commonh px
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
*commonh px
*commonh px
*commonh px
a
Starting %s Task
103*constraints2&
Connectivity Check2default:defaultZ18-103h px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
J
5Ending Logic Optimization Task | Checksum: 18ec0baab
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.282 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
a
Starting %s Task
103*constraints2&
Power Optimization2default:defaultZ18-103h px
s
7Will skip clock gating for clocks with period < %s ns.
114*pwropt2
2.002default:defaultZ34-132h px
J
5Ending Power Optimization Task | Checksum: 18ec0baab
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
\
Starting %s Task
103*constraints2!
Final Cleanup2default:defaultZ18-103h px
E
0Ending Final Cleanup Task | Checksum: 18ec0baab
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
b
Starting %s Task
103*constraints2'
Netlist Obfuscation2default:defaultZ18-103h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:002default:default2
1476.9732default:default2
0.0002default:defaultZ17-268h px
K
6Ending Netlist Obfuscation Task | Checksum: 18ec0baab
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
Z
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83h px
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28* vivadotcl2
242default:default2
02default:default2
02default:default2
02default:defaultZ4-41h px
\
%s completed successfully
29* vivadotcl2
opt_design2default:defaultZ4-42h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
opt_design: 2default:default2
00:00:262default:default2
00:00:302default:default2
1476.9732default:default2
691.0472default:defaultZ17-268h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:002default:default2
1476.9732default:default2
0.0002default:defaultZ17-268h px
H
&Writing timing data to binary archive.266*timingZ38-480h px
D
Writing placer database...
1603*designutilsZ20-1893h px
=
Writing XDEF routing.
211*designutilsZ20-211h px
J
#Writing XDEF routing logical nets.
209*designutilsZ20-209h px
J
#Writing XDEF routing special nets.
210*designutilsZ20-210h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2)
Write XDEF Complete: 2default:default2
00:00:012default:default2
00:00:00.1912default:default2
1476.9732default:default2
0.0002default:defaultZ17-268h px
The %s '%s' has been generated.
621*common2
checkpoint2default:default2K
7C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_opt.dcp2default:defaultZ17-1381h px
%s4*runtcl2o
[Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
2default:defaulth px
Command: %s
53* vivadotcl2b
Nreport_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx2default:defaultZ4-113h px
>
Refreshing IP repositories
234*coregenZ19-234h px
G
"No user IP repositories specified
1154*coregenZ19-1704h px
|
"Loaded Vivado IP repository '%s'.
1332*coregen23
C:/Xilinx/Vivado/2019.1/data/ip2default:defaultZ19-2313h px
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px
#The results of DRC are in file %s.
168*coretcl2
=C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_opted.rpt=C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_opted.rpt2default:default8Z2-168h px
\
%s completed successfully
29* vivadotcl2
report_drc2default:defaultZ4-42h px
End RecordPK
Q=D D % uart/uart.runs/impl_1/place_design.pb
Q
Command: %s
53* vivadotcl2
place_design2default:defaultZ4-113h px
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xc7z0202default:defaultZ17-347h px
0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xc7z0202default:defaultZ17-349h px
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px
V
DRC finished with %s
79* vivadotcl2
0 Errors2default:defaultZ4-198h px
e
BPlease refer to the DRC report (report_drc) for more information.
80* vivadotclZ4-199h px
p
,Running DRC as a precondition to command %s
22* vivadotcl2
place_design2default:defaultZ4-22h px
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px
V
DRC finished with %s
79* vivadotcl2
0 Errors2default:defaultZ4-198h px
e
BPlease refer to the DRC report (report_drc) for more information.
80* vivadotclZ4-199h px
U
Starting %s Task
103*constraints2
Placer2default:defaultZ18-103h px
}
BMultithreading enabled for place_design using a maximum of %s CPUs12* placeflow2
22default:defaultZ30-611h px
v
Phase %s%s
101*constraints2
1 2default:default2)
Placer Initialization2default:defaultZ18-101h px
Phase %s%s
101*constraints2
1.1 2default:default29
%Placer Initialization Netlist Sorting2default:defaultZ18-101h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:002default:default2
1476.9732default:default2
0.0002default:defaultZ17-268h px
[
FPhase 1.1 Placer Initialization Netlist Sorting | Checksum: 1489f0f38
*commonh px
%s
*constraints2s
_Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:002default:default2
1476.9732default:default2
0.0002default:defaultZ17-268h px
Phase %s%s
101*constraints2
1.2 2default:default2F
2IO Placement/ Clock Placement/ Build Placer Device2default:defaultZ18-101h px
E
%Done setting XDC timing constraints.
35*timingZ38-35h px
g
RPhase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b6a86415
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
}
Phase %s%s
101*constraints2
1.3 2default:default2.
Build Placer Netlist Model2default:defaultZ18-101h px
O
:Phase 1.3 Build Placer Netlist Model | Checksum: e0cdae93
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
z
Phase %s%s
101*constraints2
1.4 2default:default2+
Constrain Clocks/Macros2default:defaultZ18-101h px
L
7Phase 1.4 Constrain Clocks/Macros | Checksum: e0cdae93
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
H
3Phase 1 Placer Initialization | Checksum: e0cdae93
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
q
Phase %s%s
101*constraints2
2 2default:default2$
Global Placement2default:defaultZ18-101h px
p
Phase %s%s
101*constraints2
2.1 2default:default2!
Floorplanning2default:defaultZ18-101h px
C
.Phase 2.1 Floorplanning | Checksum: 19f6b6e6b
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
x
Phase %s%s
101*constraints2
2.2 2default:default2)
Global Placement Core2default:defaultZ18-101h px
Phase %s%s
101*constraints2
2.2.1 2default:default20
Physical Synthesis In Placer2default:defaultZ18-101h px
K
)No high fanout nets found in the design.
65*physynthZ32-65h px
$Optimized %s %s. Created %s new %s.
216*physynth2
02default:default2
net2default:default2
02default:default2
instance2default:defaultZ32-232h px
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px
0No setup violation found. %s was not performed.344*physynth2-
DSP Register Optimization2default:defaultZ32-670h px
0No setup violation found. %s was not performed.344*physynth2/
Shift Register Optimization2default:defaultZ32-670h px
0No setup violation found. %s was not performed.344*physynth2.
BRAM Register Optimization2default:defaultZ32-670h px
R
.No candidate nets found for HD net replication521*physynthZ32-949h px
aEnd %s Pass. Optimized %s %s. Created %s new %s, deleted %s existing %s and moved %s existing %s
415*physynth2
12default:default2
02default:default2
net or cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:default2
02default:default2
cell2default:defaultZ32-775h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:00.0012default:default2
1476.9732default:default2
0.0002default:defaultZ17-268h px
B
-
Summary of Physical Synthesis Optimizations
*commonh px
B
-============================================
*commonh px
*commonh px
*commonh px
----------------------------------------------------------------------------------------------------------------------------------------
*commonh px
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
----------------------------------------------------------------------------------------------------------------------------------------
*commonh px
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
----------------------------------------------------------------------------------------------------------------------------------------
*commonh px
*commonh px
*commonh px
T
?Phase 2.2.1 Physical Synthesis In Placer | Checksum: 115837299
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
K
6Phase 2.2 Global Placement Core | Checksum: 168c1d200
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
D
/Phase 2 Global Placement | Checksum: 168c1d200
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
q
Phase %s%s
101*constraints2
3 2default:default2$
Detail Placement2default:defaultZ18-101h px
}
Phase %s%s
101*constraints2
3.1 2default:default2.
Commit Multi Column Macros2default:defaultZ18-101h px
O
:Phase 3.1 Commit Multi Column Macros | Checksum: f3e68c54
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
Phase %s%s
101*constraints2
3.2 2default:default20
Commit Most Macros & LUTRAMs2default:defaultZ18-101h px
R
=Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14d9ca2c4
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
y
Phase %s%s
101*constraints2
3.3 2default:default2*
Area Swap Optimization2default:defaultZ18-101h px
L
7Phase 3.3 Area Swap Optimization | Checksum: 1160d7dd1
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
Phase %s%s
101*constraints2
3.4 2default:default22
Pipeline Register Optimization2default:defaultZ18-101h px
T
?Phase 3.4 Pipeline Register Optimization | Checksum: 1160d7dd1
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
Phase %s%s
101*constraints2
3.5 2default:default20
Small Shape Detail Placement2default:defaultZ18-101h px
R
=Phase 3.5 Small Shape Detail Placement | Checksum: 1c241913a
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
u
Phase %s%s
101*constraints2
3.6 2default:default2&
Re-assign LUT pins2default:defaultZ18-101h px
H
3Phase 3.6 Re-assign LUT pins | Checksum: 1ef838db3
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
Phase %s%s
101*constraints2
3.7 2default:default22
Pipeline Register Optimization2default:defaultZ18-101h px
T
?Phase 3.7 Pipeline Register Optimization | Checksum: 1ef838db3
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
D
/Phase 3 Detail Placement | Checksum: 1ef838db3
*commonh px
%s
*constraints2o
[Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.0002default:defaulth px
Phase %s%s
101*constraints2
4 2default:default2<
(Post Placement Optimization and Clean-Up2default:defaultZ18-101h px
{
Phase %s%s
101*constraints2
4.1 2default:default2,
Post Commit Optimization2default:defaultZ18-101h px
E
%Done setting XDC timing constraints.
35*timingZ38-35h px
Phase %s%s
101*constraints2
4.1.1 2default:default2/
Post Placement Optimization2default:defaultZ18-101h px
V
APost Placement Optimization Initialization | Checksum: 18ab39128
*commonh px
u
Phase %s%s
101*constraints2
4.1.1.1 2default:default2"
BUFG Insertion2default:defaultZ18-101h px
BUFG insertion identified %s candidate nets. Inserted BUFG: %s, Replicated BUFG Driver: %s, Skipped due to Placement/Routing Conflicts: %s, Skipped due to Timing Degradation: %s, Skipped due to Illegal Netlist: %s.43* placeflow2
02default:default2
02default:default2
02default:default2
02default:default2
02default:default2
02default:defaultZ46-56h px
H
3Phase 4.1.1.1 BUFG Insertion | Checksum: 18ab39128
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
hPost Placement Timing Summary WNS=%s. For the most accurate timing information please run report_timing.610*place2
4.5012default:defaultZ30-746h px
S
>Phase 4.1.1 Post Placement Optimization | Checksum: 1114a473b
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
N
9Phase 4.1 Post Commit Optimization | Checksum: 1114a473b
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
y
Phase %s%s
101*constraints2
4.2 2default:default2*
Post Placement Cleanup2default:defaultZ18-101h px
L
7Phase 4.2 Post Placement Cleanup | Checksum: 1114a473b
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
s
Phase %s%s
101*constraints2
4.3 2default:default2$
Placer Reporting2default:defaultZ18-101h px
F
1Phase 4.3 Placer Reporting | Checksum: 1114a473b
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
z
Phase %s%s
101*constraints2
4.4 2default:default2+
Final Placement Cleanup2default:defaultZ18-101h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:00.0012default:default2
1492.7662default:default2
0.0002default:defaultZ17-268h px
M
8Phase 4.4 Final Placement Cleanup | Checksum: 1551ca24d
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
\
GPhase 4 Post Placement Optimization and Clean-Up | Checksum: 1551ca24d
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
>
)Ending Placer Task | Checksum: 142ed40c7
*commonh px
%s
*constraints2p
\Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.7932default:defaulth px
Z
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83h px
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28* vivadotcl2
532default:default2
02default:default2
02default:default2
02default:defaultZ4-41h px
^
%s completed successfully
29* vivadotcl2
place_design2default:defaultZ4-42h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
place_design: 2default:default2
00:00:082default:default2
00:00:052default:default2
1492.7662default:default2
15.7932default:defaultZ17-268h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:002default:default2
1492.7662default:default2
0.0002default:defaultZ17-268h px
H
&Writing timing data to binary archive.266*timingZ38-480h px
D
Writing placer database...
1603*designutilsZ20-1893h px
=
Writing XDEF routing.
211*designutilsZ20-211h px
J
#Writing XDEF routing logical nets.
209*designutilsZ20-209h px
J
#Writing XDEF routing special nets.
210*designutilsZ20-210h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2)
Write XDEF Complete: 2default:default2
00:00:002default:default2
00:00:00.1342default:default2
1492.8162default:default2
0.0512default:defaultZ17-268h px
The %s '%s' has been generated.
621*common2
checkpoint2default:default2N
:C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_placed.dcp2default:defaultZ17-1381h px
^
%s4*runtcl2B
.Executing : report_io -file top_io_placed.rpt
2default:defaulth px
kreport_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.108 . Memory (MB): peak = 1492.816 ; gain = 0.000
*commonh px
%s4*runtcl2r
^Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
2default:defaulth px
{
%s4*runtcl2_
KExecuting : report_control_sets -verbose -file top_control_sets_placed.rpt
2default:defaulth px
ureport_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1492.816 ; gain = 0.000
*commonh px
End RecordPK
ϫQ12 2 ! uart/uart.runs/impl_1/project.wdfversion:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3633643666633931383833613435656461626365653032313364646438666332:506172656e742050412070726f6a656374204944:00
eof:3662162717
PK
Ql}7 7 % uart/uart.runs/impl_1/route_design.pb
Q
Command: %s
53* vivadotcl2
route_design2default:defaultZ4-113h px
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xc7z0202default:defaultZ17-347h px
0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xc7z0202default:defaultZ17-349h px
p
,Running DRC as a precondition to command %s
22* vivadotcl2
route_design2default:defaultZ4-22h px
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px
V
DRC finished with %s
79* vivadotcl2
0 Errors2default:defaultZ4-198h px
e
BPlease refer to the DRC report (report_drc) for more information.
80* vivadotclZ4-199h px
V
Starting %s Task
103*constraints2
Routing2default:defaultZ18-103h px
}
BMultithreading enabled for route_design using a maximum of %s CPUs17* routeflow2
22default:defaultZ35-254h px
p
Phase %s%s
101*constraints2
1 2default:default2#
Build RT Design2default:defaultZ18-101h px
C
.Phase 1 Build RT Design | Checksum: 1181bc94f
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1604.473 ; gain = 102.5982default:defaulth px
v
Phase %s%s
101*constraints2
2 2default:default2)
Router Initialization2default:defaultZ18-101h px
o
Phase %s%s
101*constraints2
2.1 2default:default2
Create Timer2default:defaultZ18-101h px
B
-Phase 2.1 Create Timer | Checksum: 1181bc94f
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1630.707 ; gain = 128.8322default:defaulth px
{
Phase %s%s
101*constraints2
2.2 2default:default2,
Fix Topology Constraints2default:defaultZ18-101h px
N
9Phase 2.2 Fix Topology Constraints | Checksum: 1181bc94f
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1637.871 ; gain = 135.9962default:defaulth px
t
Phase %s%s
101*constraints2
2.3 2default:default2%
Pre Route Cleanup2default:defaultZ18-101h px
G
2Phase 2.3 Pre Route Cleanup | Checksum: 1181bc94f
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1637.871 ; gain = 135.9962default:defaulth px
p
Phase %s%s
101*constraints2
2.4 2default:default2!
Update Timing2default:defaultZ18-101h px
C
.Phase 2.4 Update Timing | Checksum: 154732966
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:05 ; elapsed = 00:00:59 . Memory (MB): peak = 1646.301 ; gain = 144.4262default:defaulth px
Intermediate Timing Summary %s164*route2J
6| WNS=4.438 | TNS=0.000 | WHS=-0.001 | THS=-0.008 |
2default:defaultZ35-416h px
I
4Phase 2 Router Initialization | Checksum: 1b2f6b3bb
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:05 ; elapsed = 00:00:59 . Memory (MB): peak = 1646.301 ; gain = 144.4262default:defaulth px
p
Phase %s%s
101*constraints2
3 2default:default2#
Initial Routing2default:defaultZ18-101h px
C
.Phase 3 Initial Routing | Checksum: 12f3ff5fa
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
s
Phase %s%s
101*constraints2
4 2default:default2&
Rip-up And Reroute2default:defaultZ18-101h px
u
Phase %s%s
101*constraints2
4.1 2default:default2&
Global Iteration 02default:defaultZ18-101h px
Intermediate Timing Summary %s164*route2J
6| WNS=3.721 | TNS=0.000 | WHS=N/A | THS=N/A |
2default:defaultZ35-416h px
H
3Phase 4.1 Global Iteration 0 | Checksum: 19f559978
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
F
1Phase 4 Rip-up And Reroute | Checksum: 19f559978
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
|
Phase %s%s
101*constraints2
5 2default:default2/
Delay and Skew Optimization2default:defaultZ18-101h px
p
Phase %s%s
101*constraints2
5.1 2default:default2!
Delay CleanUp2default:defaultZ18-101h px
C
.Phase 5.1 Delay CleanUp | Checksum: 19f559978
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
z
Phase %s%s
101*constraints2
5.2 2default:default2+
Clock Skew Optimization2default:defaultZ18-101h px
M
8Phase 5.2 Clock Skew Optimization | Checksum: 19f559978
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
O
:Phase 5 Delay and Skew Optimization | Checksum: 19f559978
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
n
Phase %s%s
101*constraints2
6 2default:default2!
Post Hold Fix2default:defaultZ18-101h px
p
Phase %s%s
101*constraints2
6.1 2default:default2!
Hold Fix Iter2default:defaultZ18-101h px
r
Phase %s%s
101*constraints2
6.1.1 2default:default2!
Update Timing2default:defaultZ18-101h px
E
0Phase 6.1.1 Update Timing | Checksum: 1afe203b4
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
Intermediate Timing Summary %s164*route2J
6| WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
2default:defaultZ35-416h px
C
.Phase 6.1 Hold Fix Iter | Checksum: 1afe203b4
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
A
,Phase 6 Post Hold Fix | Checksum: 1afe203b4
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
o
Phase %s%s
101*constraints2
7 2default:default2"
Route finalize2default:defaultZ18-101h px
B
-Phase 7 Route finalize | Checksum: 1afe203b4
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.5472default:defaulth px
v
Phase %s%s
101*constraints2
8 2default:default2)
Verifying routed nets2default:defaultZ18-101h px
I
4Phase 8 Verifying routed nets | Checksum: 1afe203b4
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.5862default:defaulth px
r
Phase %s%s
101*constraints2
9 2default:default2%
Depositing Routes2default:defaultZ18-101h px
E
0Phase 9 Depositing Routes | Checksum: 1e8cc58ed
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.5862default:defaulth px
t
Phase %s%s
101*constraints2
10 2default:default2&
Post Router Timing2default:defaultZ18-101h px
Estimated Timing Summary %s
57*route2J
6| WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
2default:defaultZ35-57h px
The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
127*routeZ35-327h px
G
2Phase 10 Post Router Timing | Checksum: 1e8cc58ed
*commonh px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.5862default:defaulth px
@
Router Completed Successfully
2* routeflowZ35-16h px
%s
*constraints2q
]Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.5862default:defaulth px
Z
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83h px
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28* vivadotcl2
702default:default2
02default:default2
02default:default2
02default:defaultZ4-41h px
^
%s completed successfully
29* vivadotcl2
route_design2default:defaultZ4-42h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
route_design: 2default:default2
00:01:092default:default2
00:01:012default:default2
1650.4612default:default2
157.6452default:defaultZ17-268h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2.
Netlist sorting complete. 2default:default2
00:00:002default:default2
00:00:00.0012default:default2
1650.4612default:default2
0.0002default:defaultZ17-268h px
H
&Writing timing data to binary archive.266*timingZ38-480h px
D
Writing placer database...
1603*designutilsZ20-1893h px
=
Writing XDEF routing.
211*designutilsZ20-211h px
J
#Writing XDEF routing logical nets.
209*designutilsZ20-209h px
J
#Writing XDEF routing special nets.
210*designutilsZ20-210h px
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2)
Write XDEF Complete: 2default:default2
00:00:002default:default2
00:00:00.1392default:default2
1660.3632default:default2
9.9022default:defaultZ17-268h px
The %s '%s' has been generated.
621*common2
checkpoint2default:default2N
:C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_routed.dcp2default:defaultZ17-1381h px
%s4*runtcl2r
^Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
2default:defaulth px
Command: %s
53* vivadotcl2e
Qreport_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx2default:defaultZ4-113h px
>
IP Catalog is up to date.1232*coregenZ19-1839h px
P
Running DRC with %s threads
24*drc2
22default:defaultZ23-27h px
#The results of DRC are in file %s.
168*coretcl2
>C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_routed.rpt>C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_routed.rpt2default:default8Z2-168h px
\
%s completed successfully
29* vivadotcl2
report_drc2default:defaultZ4-42h px
%s4*runtcl2
Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
2default:defaulth px
Command: %s
53* vivadotcl2
}report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx2default:defaultZ4-113h px
E
%Done setting XDC timing constraints.
35*timingZ38-35h px
Y
$Running Methodology with %s threads
74*drc2
22default:defaultZ23-133h px
2The results of Report Methodology are in file %s.
450*coretcl2
JC:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_methodology_drc_routed.rptJC:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_methodology_drc_routed.rpt2default:default8Z2-1520h px
d
%s completed successfully
29* vivadotcl2&
report_methodology2default:defaultZ4-42h px
%s4*runtcl2
nExecuting : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
2default:defaulth px
Command: %s
53* vivadotcl2u
areport_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx2default:defaultZ4-113h px
E
%Done setting XDC timing constraints.
35*timingZ38-35h px
K
,Running Vector-less Activity Propagation...
51*powerZ33-51h px
P
3
Finished Running Vector-less Activity Propagation
1*powerZ33-1h px
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28* vivadotcl2
822default:default2
02default:default2
02default:default2
02default:defaultZ4-41h px
^
%s completed successfully
29* vivadotcl2
report_power2default:defaultZ4-42h px
%s4*runtcl2g
SExecuting : report_route_status -file top_route_status.rpt -pb top_route_status.pb
2default:defaulth px
%s4*runtcl2
Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation
2default:defaulth px
r
UpdateTimingParams:%s.
91*timing29
% Speed grade: -1, Delay Type: min_max2default:defaultZ38-91h px
|
CMultithreading enabled for timing update using a maximum of %s CPUs155*timing2
22default:defaultZ38-191h px
|
%s4*runtcl2`
LExecuting : report_incremental_reuse -file top_incremental_reuse_routed.rpt
2default:defaulth px
g
BIncremental flow is disabled. No incremental reuse Info to report.423* vivadotclZ4-1062h px
|
%s4*runtcl2`
LExecuting : report_clock_utilization -file top_clock_utilization_routed.rpt
2default:defaulth px
%s4*runtcl2
Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
2default:defaulth px
r
UpdateTimingParams:%s.
91*timing29
% Speed grade: -1, Delay Type: min_max2default:defaultZ38-91h px
|
CMultithreading enabled for timing update using a maximum of %s CPUs155*timing2
22default:defaultZ38-191h px
End RecordPK
ϫQ2qh h uart/uart.runs/impl_1/rundef.js//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
} else {
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
// pre-commands:
ISETouchFile( "init_design", "begin" );
ISEStep( "vivado",
"-log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
PK
ϫQ| uart/uart.runs/impl_1/runme.bat@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
PK
Qrr r uart/uart.runs/impl_1/runme.log
*** Running vivado
with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
****** Vivado v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source top.tcl -notrace
Command: link_design -top top -part xc7z020clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc]
Finished Parsing XDC File [C:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 781.891 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 785.926 ; gain = 415.062
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 803.875 ; gain = 17.949
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 2190fe924
Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1333.379 ; gain = 529.504
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 2190fe924
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.160 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 2190fe924
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.165 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.204 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.218 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.227 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.231 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1476.973 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.282 . Memory (MB): peak = 1476.973 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1476.973 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 1476.973 ; gain = 691.047
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.191 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1489f0f38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1476.973 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b6a86415
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 19f6b6e6b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2.2 Global Placement Core
Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1476.973 ; gain = 0.000
Summary of Physical Synthesis Optimizations
============================================
----------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
----------------------------------------------------------------------------------------------------------------------------------------
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
----------------------------------------------------------------------------------------------------------------------------------------
Phase 2.2.1 Physical Synthesis In Placer | Checksum: 115837299
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2.2 Global Placement Core | Checksum: 168c1d200
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2 Global Placement | Checksum: 168c1d200
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: f3e68c54
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14d9ca2c4
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1160d7dd1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1160d7dd1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1c241913a
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 18ab39128
Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 18ab39128
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
INFO: [Place 30-746] Post Placement Timing Summary WNS=4.501. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.1 Post Commit Optimization | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1492.766 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1551ca24d
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1551ca24d
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Ending Placer Task | Checksum: 142ed40c7
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1492.766 ; gain = 15.793
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1492.766 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.134 . Memory (MB): peak = 1492.816 ; gain = 0.051
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.108 . Memory (MB): peak = 1492.816 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1492.816 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 9563aad4 ConstDB: 0 ShapeSum: ad8995f3 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1604.473 ; gain = 102.598
Post Restoration Checksum: NetGraph: 60cb6e48 NumContArr: b7505b07 Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1630.707 ; gain = 128.832
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1637.871 ; gain = 135.996
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1637.871 ; gain = 135.996
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 154732966
Time (s): cpu = 00:01:05 ; elapsed = 00:00:59 . Memory (MB): peak = 1646.301 ; gain = 144.426
INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.438 | TNS=0.000 | WHS=-0.001 | THS=-0.008 |
Phase 2 Router Initialization | Checksum: 1b2f6b3bb
Time (s): cpu = 00:01:05 ; elapsed = 00:00:59 . Memory (MB): peak = 1646.301 ; gain = 144.426
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 44
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 44
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 12f3ff5fa
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.721 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 4 Rip-up And Reroute | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 5 Delay and Skew Optimization | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 6 Post Hold Fix | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.00295123 %
Global Horizontal Routing Utilization = 0.0015213 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1e8cc58ed
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1e8cc58ed
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
70 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:09 ; elapsed = 00:01:01 . Memory (MB): peak = 1650.461 ; gain = 157.645
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1650.461 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 1660.363 ; gain = 9.902
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
82 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 2 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: LED.
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
98 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
write_bitstream failed
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
INFO: [Common 17-206] Exiting Vivado at Tue Dec 22 21:32:53 2020...
PK
ϫQF~ uart/uart.runs/impl_1/runme.sh#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
echo "This script was generated under a different operating system."
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
exit
if [ -z "$PATH" ]; then
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
else
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='C:/Users/renhe/xilinx/uart/uart.runs/impl_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
# pre-commands:
/bin/touch .init_design.begin.rst
EAStep vivado -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
PK
ϫQB` ` uart/uart.runs/impl_1/top.tcl#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch ""
puts $ch ""
puts $ch " "
puts $ch " "
puts $ch ""
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
set_msg_config -id {Common 17-41} -limit 10000000
set_msg_config -id {HDL-1065} -limit 10000
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param chipscope.maxJobs 2
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7z020clg400-1
set_property board_part_repo_paths {C:/Users/renhe/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store} [current_project]
set_property board_part digilentinc.com:arty-z7-20:part0:1.0 [current_project]
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir C:/Users/renhe/xilinx/uart/uart.cache/wt [current_project]
set_property parent.project_path C:/Users/renhe/xilinx/uart/uart.xpr [current_project]
set_property ip_output_repo C:/Users/renhe/xilinx/uart/uart.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet C:/Users/renhe/xilinx/uart/uart.runs/synth_1/top.dcp
read_xdc C:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc
link_design -top top -part xc7z020clg400-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force top_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force top_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file top_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file top_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force top_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file top_route_status.rpt -pb top_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file top_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file top_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force top_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
catch { write_mem_info -force top.mmi }
write_bitstream -force top.bit
catch {write_debug_probes -quiet -force top}
catch {file copy -force top.ltx debug_nets.ltx}
close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
step_failed write_bitstream
return -code error $RESULT
} else {
end_step write_bitstream
unset ACTIVE_STEP
}
PK
Q1Vq q uart/uart.runs/impl_1/top.vdi#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Tue Dec 22 21:30:35 2020
# Process ID: 8092
# Current directory: C:/Users/renhe/xilinx/uart/uart.runs/impl_1
# Command line: vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
# Log file: C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top.vdi
# Journal file: C:/Users/renhe/xilinx/uart/uart.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source top.tcl -notrace
Command: link_design -top top -part xc7z020clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc]
Finished Parsing XDC File [C:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 781.891 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 785.926 ; gain = 415.062
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 803.875 ; gain = 17.949
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 2190fe924
Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1333.379 ; gain = 529.504
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 2190fe924
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.160 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 2190fe924
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.165 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.204 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.218 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.227 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.231 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1476.973 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.282 . Memory (MB): peak = 1476.973 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1476.973 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 1476.973 ; gain = 691.047
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.191 . Memory (MB): peak = 1476.973 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1489f0f38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1476.973 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b6a86415
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 19f6b6e6b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2.2 Global Placement Core
Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1476.973 ; gain = 0.000
Summary of Physical Synthesis Optimizations
============================================
----------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
----------------------------------------------------------------------------------------------------------------------------------------
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
----------------------------------------------------------------------------------------------------------------------------------------
Phase 2.2.1 Physical Synthesis In Placer | Checksum: 115837299
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2.2 Global Placement Core | Checksum: 168c1d200
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 2 Global Placement | Checksum: 168c1d200
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: f3e68c54
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14d9ca2c4
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1160d7dd1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1160d7dd1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1c241913a
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1476.973 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 18ab39128
Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 18ab39128
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
INFO: [Place 30-746] Post Placement Timing Summary WNS=4.501. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.1 Post Commit Optimization | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1492.766 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1551ca24d
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1551ca24d
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
Ending Placer Task | Checksum: 142ed40c7
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1492.766 ; gain = 15.793
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1492.766 ; gain = 15.793
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1492.766 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.134 . Memory (MB): peak = 1492.816 ; gain = 0.051
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.108 . Memory (MB): peak = 1492.816 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1492.816 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 9563aad4 ConstDB: 0 ShapeSum: ad8995f3 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1604.473 ; gain = 102.598
Post Restoration Checksum: NetGraph: 60cb6e48 NumContArr: b7505b07 Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1630.707 ; gain = 128.832
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1637.871 ; gain = 135.996
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 1181bc94f
Time (s): cpu = 00:01:05 ; elapsed = 00:00:58 . Memory (MB): peak = 1637.871 ; gain = 135.996
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 154732966
Time (s): cpu = 00:01:05 ; elapsed = 00:00:59 . Memory (MB): peak = 1646.301 ; gain = 144.426
INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.438 | TNS=0.000 | WHS=-0.001 | THS=-0.008 |
Phase 2 Router Initialization | Checksum: 1b2f6b3bb
Time (s): cpu = 00:01:05 ; elapsed = 00:00:59 . Memory (MB): peak = 1646.301 ; gain = 144.426
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 44
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 44
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 12f3ff5fa
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.721 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 4 Rip-up And Reroute | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 5 Delay and Skew Optimization | Checksum: 19f559978
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 6 Post Hold Fix | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.00295123 %
Global Horizontal Routing Utilization = 0.0015213 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1648.422 ; gain = 146.547
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1afe203b4
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1e8cc58ed
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1e8cc58ed
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:01:06 ; elapsed = 00:00:59 . Memory (MB): peak = 1650.461 ; gain = 148.586
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
70 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:09 ; elapsed = 00:01:01 . Memory (MB): peak = 1650.461 ; gain = 157.645
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1650.461 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 1660.363 ; gain = 9.902
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
82 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 2 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: LED.
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
98 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
write_bitstream failed
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
INFO: [Common 17-206] Exiting Vivado at Tue Dec 22 21:32:53 2020...
PK
+Q-j j ) uart/uart.runs/impl_1/top_7752.backup.vdi#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Tue Dec 22 21:23:30 2020
# Process ID: 7752
# Current directory: C:/Users/renhe/xilinx/uart/uart.runs/impl_1
# Command line: vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace
# Log file: C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top.vdi
# Journal file: C:/Users/renhe/xilinx/uart/uart.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source top.tcl -notrace
Command: link_design -top top -part xc7z020clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc]
Finished Parsing XDC File [C:/Users/renhe/xilinx/uart/uart.srcs/constrs_1/imports/Desktop/Arty-Z7-20-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 781.516 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 785.535 ; gain = 414.867
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 802.535 ; gain = 17.000
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 2190fe924
Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1332.746 ; gain = 530.211
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 2190fe924
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 2190fe924
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 2608436f6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1480.410 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.100 . Memory (MB): peak = 1480.410 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1480.410 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1480.410 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1480.410 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 18ec0baab
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 1480.410 ; gain = 694.875
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 1480.410 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1489f0f38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1480.410 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b6a86415
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: e0cdae93
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 19f6b6e6b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 2.2 Global Placement Core
Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1480.410 ; gain = 0.000
Summary of Physical Synthesis Optimizations
============================================
----------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
----------------------------------------------------------------------------------------------------------------------------------------
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
----------------------------------------------------------------------------------------------------------------------------------------
Phase 2.2.1 Physical Synthesis In Placer | Checksum: 115837299
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 2.2 Global Placement Core | Checksum: 168c1d200
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 2 Global Placement | Checksum: 168c1d200
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: f3e68c54
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14d9ca2c4
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1160d7dd1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1160d7dd1
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1c241913a
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1ef838db3
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1480.410 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 18ab39128
Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 18ab39128
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
INFO: [Place 30-746] Post Placement Timing Summary WNS=4.501. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
Phase 4.1 Post Commit Optimization | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1114a473b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1496.211 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1551ca24d
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1551ca24d
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
Ending Placer Task | Checksum: 142ed40c7
Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1496.211 ; gain = 15.801
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 1496.211 ; gain = 15.801
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1496.211 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 1496.211 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.104 . Memory (MB): peak = 1496.211 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1496.211 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 9563aad4 ConstDB: 0 ShapeSum: ad8995f3 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1181bc94f
Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 1602.574 ; gain = 97.254
Post Restoration Checksum: NetGraph: 60cb6e48 NumContArr: b7505b07 Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 1181bc94f
Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 1628.789 ; gain = 123.469
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 1181bc94f
Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 1636.082 ; gain = 130.762
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 1181bc94f
Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 1636.082 ; gain = 130.762
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 154732966
Time (s): cpu = 00:00:50 ; elapsed = 00:00:48 . Memory (MB): peak = 1644.484 ; gain = 139.164
INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.438 | TNS=0.000 | WHS=-0.001 | THS=-0.008 |
Phase 2 Router Initialization | Checksum: 1b2f6b3bb
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1644.484 ; gain = 139.164
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 44
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 44
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 12f3ff5fa
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.721 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 19f559978
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 4 Rip-up And Reroute | Checksum: 19f559978
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 19f559978
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 19f559978
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 5 Delay and Skew Optimization | Checksum: 19f559978
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1afe203b4
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1afe203b4
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 6 Post Hold Fix | Checksum: 1afe203b4
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.00295123 %
Global Horizontal Routing Utilization = 0.0015213 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1afe203b4
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1645.754 ; gain = 140.434
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1afe203b4
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1647.785 ; gain = 142.465
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1e8cc58ed
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1647.785 ; gain = 142.465
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.874 | TNS=0.000 | WHS=0.248 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1e8cc58ed
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1647.785 ; gain = 142.465
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:51 ; elapsed = 00:00:48 . Memory (MB): peak = 1647.785 ; gain = 142.465
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
70 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:50 . Memory (MB): peak = 1647.785 ; gain = 151.574
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1647.785 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.126 . Memory (MB): peak = 1657.676 ; gain = 9.891
INFO: [Common 17-1381] The checkpoint 'C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/renhe/xilinx/uart/uart.runs/impl_1/top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
82 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file top_route_status.rpt -pb top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Tue Dec 22 21:25:21 2020...
PK
QP , uart/uart.runs/impl_1/top_bus_skew_routed.pb
2018.1Bus skew results PK
Q8ت= = - uart/uart.runs/impl_1/top_bus_skew_routed.rptCopyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date : Tue Dec 22 21:32:49 2020
| Host : DESKTOP-UPJ0SJJ running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
| Design : top
| Device : 7z020-clg400
| Speed File : -1 PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints
PK
Qh - uart/uart.runs/impl_1/top_bus_skew_routed.rpx( 2018.1"BusSkewSummary"PB_RTBusSkew
2018.1Bus skew results !
Bus Skew Reportxreport_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpxns"MHz(0:
ReportBus Skew Report
Designtop
K
PartCDevice=7z020 Package=clg400 Speed=-1 (PRODUCTION 1.11 2014-09-11)
T
VersionIVivado v2019.1 (64-bit) SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
DateTue Dec 22 21:32:49 2020
Commandxreport_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpxBbus skew reportV
-1 min_max (0 8@H X` h p x Zmin_maxbslackhp}IIqxreport_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx
0
(knN ( 0 8 @ H UIqPK
Qv=) ) 6 uart/uart.runs/impl_1/top_clock_utilization_routed.rptCopyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date : Tue Dec 22 21:32:49 2020
| Host : DESKTOP-UPJ0SJJ running 64-bit major release (build 9200)
| Command : report_clock_utilization -file top_clock_utilization_routed.rpt
| Design : top
| Device : 7z020-clg400
| Speed File : -1 PRODUCTION 1.11 2014-09-11
| Design State : Routed
------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y0
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 72 | 0 | 0 | 0 |
| BUFIO | 0 | 16 | 0 | 0 | 0 |
| BUFMR | 0 | 8 | 0 | 0 | 0 |
| BUFR | 0 | 16 | 0 | 0 | 0 |
| MMCM | 0 | 4 | 0 | 0 | 0 |
| PLL | 0 | 4 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 33 | 0 | 8.000 | sys_clk_pin | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | IOB_X1Y124 | IOB_X1Y124 | X1Y2 | 1 | 0 | 8.000 | sys_clk_pin | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 33 | 2500 | 33 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
| X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 1 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | sys_clk_pin | 8.000 | {0.000 4.000} | 33 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-----+----+
| | X0 | X1 |
+----+-----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 33 | 0 |
+----+-----+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y0
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 33 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X1Y124 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
#endgroup
PK
QM` ` 1 uart/uart.runs/impl_1/top_control_sets_placed.rptCopyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date : Tue Dec 22 21:31:42 2020
| Host : DESKTOP-UPJ0SJJ running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file top_control_sets_placed.rpt
| Design : top
| Device : xc7z020
------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Total control sets | 2 |
| Minimum number of control sets | 2 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
| Unused register locations in slices containing registers | 7 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
2. Histogram
------------
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
| Total control sets | 2 |
| >= 0 to < 4 | 1 |
| >= 4 to < 6 | 0 |
| >= 6 to < 8 | 0 |
| >= 8 to < 10 | 0 |
| >= 10 to < 12 | 0 |
| >= 12 to < 14 | 0 |
| >= 14 to < 16 | 0 |
| >= 16 | 1 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 1 | 1 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 32 | 8 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+---------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+---------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | | | 1 | 1 |
| clk_IBUF_BUFG | | clear | 8 | 32 |
+----------------+---------------+------------------+------------------+----------------+
PK
QO% % &