*** Running vivado with args -log user_35t_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source user_35t_wrapper.tcl -notrace ****** Vivado v2016.4 (64-bit) **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017 **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source user_35t_wrapper.tcl -notrace Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_emc_0_0/user_35t_axi_emc_0_0.dcp' for cell 'user_35t_i/axi_emc_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0.dcp' for cell 'user_35t_i/axi_gpio_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0.dcp' for cell 'user_35t_i/axi_gpio_1' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_intc_0_0/user_35t_axi_intc_0_0.dcp' for cell 'user_35t_i/axi_intc_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_timer_0_0/user_35t_axi_timer_0_0.dcp' for cell 'user_35t_i/axi_timer_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_uartlite_0_0/user_35t_axi_uartlite_0_0.dcp' for cell 'user_35t_i/axi_uartlite_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.dcp' for cell 'user_35t_i/clk_wiz_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_mdm_1_0/user_35t_mdm_1_0.dcp' for cell 'user_35t_i/mdm_1' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_microblaze_0_0/user_35t_microblaze_0_0.dcp' for cell 'user_35t_i/microblaze_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_rst_clk_wiz_0_100M_0/user_35t_rst_clk_wiz_0_100M_0.dcp' for cell 'user_35t_i/rst_clk_wiz_0_100M' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_xlconcat_0_0/user_35t_xlconcat_0_0.dcp' for cell 'user_35t_i/xlconcat_0' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_xbar_0/user_35t_xbar_0.dcp' for cell 'user_35t_i/axi_mem_intercon/xbar' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_m00_data_fifo_0/user_35t_m00_data_fifo_0.dcp' for cell 'user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_m00_regslice_0/user_35t_m00_regslice_0.dcp' for cell 'user_35t_i/axi_mem_intercon/m00_couplers/m00_regslice' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s00_data_fifo_0/user_35t_s00_data_fifo_0.dcp' for cell 'user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s00_regslice_0/user_35t_s00_regslice_0.dcp' for cell 'user_35t_i/axi_mem_intercon/s00_couplers/s00_regslice' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s01_data_fifo_0/user_35t_s01_data_fifo_0.dcp' for cell 'user_35t_i/axi_mem_intercon/s01_couplers/s01_data_fifo' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s01_regslice_0/user_35t_s01_regslice_0.dcp' for cell 'user_35t_i/axi_mem_intercon/s01_couplers/s01_regslice' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_xbar_1/user_35t_xbar_1.dcp' for cell 'user_35t_i/microblaze_0_axi_periph/xbar' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_dlmb_bram_if_cntlr_0/user_35t_dlmb_bram_if_cntlr_0.dcp' for cell 'user_35t_i/microblaze_0_local_memory/dlmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_dlmb_v10_0/user_35t_dlmb_v10_0.dcp' for cell 'user_35t_i/microblaze_0_local_memory/dlmb_v10' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_ilmb_bram_if_cntlr_0/user_35t_ilmb_bram_if_cntlr_0.dcp' for cell 'user_35t_i/microblaze_0_local_memory/ilmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_ilmb_v10_0/user_35t_ilmb_v10_0.dcp' for cell 'user_35t_i/microblaze_0_local_memory/ilmb_v10' INFO: [Project 1-454] Reading design checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_lmb_bram_0/user_35t_lmb_bram_0.dcp' for cell 'user_35t_i/microblaze_0_local_memory/lmb_bram' INFO: [Netlist 29-17] Analyzing 387 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2016.4 INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37402] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[10]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37472] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[11]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37479] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[12]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37486] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[13]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37493] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[14]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37500] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[15]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37507] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[16]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37514] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[17]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37521] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[18]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37528] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[1]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37409] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[2]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37416] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[3]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37423] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[4]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37430] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[5]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37437] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[6]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37444] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[7]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37451] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[8]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37458] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[9]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37465] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_cen[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37613] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37703] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[1]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37710] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[2]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37717] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[3]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37724] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[4]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37731] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[5]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37738] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[6]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37745] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[7]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37752] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_oen[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37760] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_wen' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37307] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_gpio_0/gpio2_io_i[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_3/user_35t_axi_gpio_0_0.edf:5823] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_gpio_0/gpio_io_t[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_3/user_35t_axi_gpio_0_0.edf:5853] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_gpio_0/gpio_io_t[1]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_3/user_35t_axi_gpio_0_0.edf:5860] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_gpio_1/gpio_io_t[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_4/user_35t_axi_gpio_1_0.edf:3416] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_gpio_1/gpio_io_t[1]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_4/user_35t_axi_gpio_1_0.edf:3423] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_gpio_1/gpio_io_t[2]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_4/user_35t_axi_gpio_1_0.edf:3430] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_uartlite_0/rx' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_7/user_35t_axi_uartlite_0_0.edf:7818] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_uartlite_0/tx' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_7/user_35t_axi_uartlite_0_0.edf:7885] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/clk_wiz_0/reset' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_8/user_35t_clk_wiz_0_0.edf:315] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/rst_clk_wiz_0_100M/ext_reset_in' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_16/user_35t_rst_clk_wiz_0_100M_0.edf:1546] Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_emc_0_0/user_35t_axi_emc_0_0_board.xdc] for cell 'user_35t_i/axi_emc_0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_emc_0_0/user_35t_axi_emc_0_0_board.xdc] for cell 'user_35t_i/axi_emc_0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_emc_0_0/user_35t_axi_emc_0_0.xdc] for cell 'user_35t_i/axi_emc_0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_emc_0_0/user_35t_axi_emc_0_0.xdc] for cell 'user_35t_i/axi_emc_0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0_board.xdc] for cell 'user_35t_i/axi_gpio_0/U0' CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0_board.xdc:3] Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced. CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0_board.xdc:5] Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced. Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0_board.xdc] for cell 'user_35t_i/axi_gpio_0/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0.xdc] for cell 'user_35t_i/axi_gpio_0/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0.xdc] for cell 'user_35t_i/axi_gpio_0/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0_board.xdc] for cell 'user_35t_i/axi_gpio_1/U0' CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0_board.xdc:3] Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced. CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0_board.xdc:5] Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced. CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0_board.xdc:7] Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced. Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0_board.xdc] for cell 'user_35t_i/axi_gpio_1/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0.xdc] for cell 'user_35t_i/axi_gpio_1/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0.xdc] for cell 'user_35t_i/axi_gpio_1/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_intc_0_0/user_35t_axi_intc_0_0.xdc] for cell 'user_35t_i/axi_intc_0/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_intc_0_0/user_35t_axi_intc_0_0.xdc] for cell 'user_35t_i/axi_intc_0/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_timer_0_0/user_35t_axi_timer_0_0.xdc] for cell 'user_35t_i/axi_timer_0/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_timer_0_0/user_35t_axi_timer_0_0.xdc] for cell 'user_35t_i/axi_timer_0/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_uartlite_0_0/user_35t_axi_uartlite_0_0_board.xdc] for cell 'user_35t_i/axi_uartlite_0/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_uartlite_0_0/user_35t_axi_uartlite_0_0_board.xdc] for cell 'user_35t_i/axi_uartlite_0/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_uartlite_0_0/user_35t_axi_uartlite_0_0.xdc] for cell 'user_35t_i/axi_uartlite_0/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_uartlite_0_0/user_35t_axi_uartlite_0_0.xdc] for cell 'user_35t_i/axi_uartlite_0/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0_board.xdc] for cell 'user_35t_i/clk_wiz_0/inst' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0_board.xdc] for cell 'user_35t_i/clk_wiz_0/inst' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.xdc] for cell 'user_35t_i/clk_wiz_0/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.xdc:57] get_clocks: Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1015.875 ; gain = 477.027 WARNING: [Vivado 12-2489] -input_jitter contains time 0.833330 which will be rounded to 0.833 to ensure it is an integer multiple of 1 picosecond [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.xdc:57] Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.xdc] for cell 'user_35t_i/clk_wiz_0/inst' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_mdm_1_0/user_35t_mdm_1_0.xdc] for cell 'user_35t_i/mdm_1/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_mdm_1_0/user_35t_mdm_1_0.xdc] for cell 'user_35t_i/mdm_1/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_microblaze_0_0/user_35t_microblaze_0_0.xdc] for cell 'user_35t_i/microblaze_0/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_microblaze_0_0/user_35t_microblaze_0_0.xdc] for cell 'user_35t_i/microblaze_0/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_dlmb_v10_0/user_35t_dlmb_v10_0.xdc] for cell 'user_35t_i/microblaze_0_local_memory/dlmb_v10/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_dlmb_v10_0/user_35t_dlmb_v10_0.xdc] for cell 'user_35t_i/microblaze_0_local_memory/dlmb_v10/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_ilmb_v10_0/user_35t_ilmb_v10_0.xdc] for cell 'user_35t_i/microblaze_0_local_memory/ilmb_v10/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_ilmb_v10_0/user_35t_ilmb_v10_0.xdc] for cell 'user_35t_i/microblaze_0_local_memory/ilmb_v10/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_rst_clk_wiz_0_100M_0/user_35t_rst_clk_wiz_0_100M_0_board.xdc] for cell 'user_35t_i/rst_clk_wiz_0_100M/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_rst_clk_wiz_0_100M_0/user_35t_rst_clk_wiz_0_100M_0_board.xdc] for cell 'user_35t_i/rst_clk_wiz_0_100M/U0' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_rst_clk_wiz_0_100M_0/user_35t_rst_clk_wiz_0_100M_0.xdc] for cell 'user_35t_i/rst_clk_wiz_0_100M/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_rst_clk_wiz_0_100M_0/user_35t_rst_clk_wiz_0_100M_0.xdc] for cell 'user_35t_i/rst_clk_wiz_0_100M/U0' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_emc_0_0/user_35t_axi_emc_0_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_0_0/user_35t_axi_gpio_0_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_gpio_1_0/user_35t_axi_gpio_1_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_intc_0_0/user_35t_axi_intc_0_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_timer_0_0/user_35t_axi_timer_0_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_uartlite_0_0/user_35t_axi_uartlite_0_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_mdm_1_0/user_35t_mdm_1_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_microblaze_0_0/user_35t_microblaze_0_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_dlmb_bram_if_cntlr_0/user_35t_dlmb_bram_if_cntlr_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_dlmb_v10_0/user_35t_dlmb_v10_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_ilmb_bram_if_cntlr_0/user_35t_ilmb_bram_if_cntlr_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_ilmb_v10_0/user_35t_ilmb_v10_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_lmb_bram_0/user_35t_lmb_bram_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_rst_clk_wiz_0_100M_0/user_35t_rst_clk_wiz_0_100M_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_xbar_0/user_35t_xbar_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_xbar_1/user_35t_xbar_1.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s00_regslice_0/user_35t_s00_regslice_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s00_data_fifo_0/user_35t_s00_data_fifo_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s01_regslice_0/user_35t_s01_regslice_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_s01_data_fifo_0/user_35t_s01_data_fifo_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_m00_data_fifo_0/user_35t_m00_data_fifo_0.dcp' INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_m00_regslice_0/user_35t_m00_regslice_0.dcp' Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_intc_0_0/user_35t_axi_intc_0_0_clocks.xdc] for cell 'user_35t_i/axi_intc_0/U0' Finished Parsing XDC File [d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_axi_intc_0_0/user_35t_axi_intc_0_0_clocks.xdc] for cell 'user_35t_i/axi_intc_0/U0' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Generating merged BMM file for the design top 'user_35t_wrapper'... INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: d:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_microblaze_0_0/data/mb_bootloop_le.elf INFO: [Project 1-111] Unisim Transformation Summary: A total of 191 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 71 instances RAM32X1D => RAM32X1D (RAMD32, RAMD32): 32 instances link_design: Time (s): cpu = 00:01:13 ; elapsed = 00:01:22 . Memory (MB): peak = 1015.973 ; gain = 805.715 Command: opt_design -directive RuntimeOptimized INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1015.973 ; gain = 0.000 Starting Logic Optimization Task Implement Debug Cores | Checksum: 14752dbbf INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Retarget INFO: [Opt 31-138] Pushed 6 inverter(s) to 20 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 8ab6350b Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1020.266 ; gain = 4.293 Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-10] Eliminated 359 cells. Phase 2 Constant propagation | Checksum: 12d930445 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1020.266 ; gain = 4.293 Phase 3 Sweep INFO: [Opt 31-12] Eliminated 2637 unconnected nets. INFO: [Opt 31-11] Eliminated 1442 unconnected cells. Phase 3 Sweep | Checksum: 127b2d17d Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1020.266 ; gain = 4.293 Phase 4 BUFG optimization INFO: [Opt 31-12] Eliminated 0 unconnected nets. INFO: [Opt 31-11] Eliminated 0 unconnected cells. Phase 4 BUFG optimization | Checksum: 32f1a3b8 Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1020.266 ; gain = 4.293 Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 1020.266 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 32f1a3b8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 1020.266 ; gain = 4.293 INFO: [Common 17-83] Releasing license: Implementation 72 Infos, 41 Warnings, 5 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1020.266 ; gain = 4.293 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.470 . Memory (MB): peak = 1020.266 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/user_35t_wrapper_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 1020.266 ; gain = 0.000 INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/user_35t_wrapper_drc_opted.rpt. report_drc: Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 1020.266 ; gain = 0.000 INFO: [Chipscope 16-241] No debug cores found in the current design. Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. Command: place_design -directive RuntimeOptimized Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ENBWREN (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[0] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[1] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[2] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[3] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[4] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[5] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[6] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[7] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ENARDEN (net: user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/gpregsm1.curr_fwft_state_reg[1]) which is driven by a register (user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 10 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.132 . Memory (MB): peak = 1020.266 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 1020.266 ; gain = 0.000 Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12c37495c Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1040.500 ; gain = 20.234 Phase 1.2 Build Placer Netlist Model Phase 1.2 Build Placer Netlist Model | Checksum: 206832b1d Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 1.3 Constrain Clocks/Macros Phase 1.3 Constrain Clocks/Macros | Checksum: 206832b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 1 Placer Initialization | Checksum: 206832b1d Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 2 Global Placement Phase 2 Global Placement | Checksum: 1cdd0ff2d Time (s): cpu = 00:01:12 ; elapsed = 00:00:50 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1cdd0ff2d Time (s): cpu = 00:01:13 ; elapsed = 00:00:51 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 181caf0e0 Time (s): cpu = 00:01:25 ; elapsed = 00:00:59 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ae8e0a75 Time (s): cpu = 00:01:26 ; elapsed = 00:00:59 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1700fb46a Time (s): cpu = 00:01:26 ; elapsed = 00:00:59 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3.5 Timing Path Optimizer Phase 3.5 Timing Path Optimizer | Checksum: 120885cb7 Time (s): cpu = 00:01:30 ; elapsed = 00:01:02 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 179059ba7 Time (s): cpu = 00:01:42 ; elapsed = 00:01:14 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 11cdd3fc6 Time (s): cpu = 00:01:43 ; elapsed = 00:01:16 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 122b91fc0 Time (s): cpu = 00:01:44 ; elapsed = 00:01:16 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 3 Detail Placement | Checksum: 122b91fc0 Time (s): cpu = 00:01:44 ; elapsed = 00:01:16 . Memory (MB): peak = 1050.898 ; gain = 30.633 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.505. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 1e19d0f6e Time (s): cpu = 00:02:00 ; elapsed = 00:01:26 . Memory (MB): peak = 1065.418 ; gain = 45.152 Phase 4.1 Post Commit Optimization | Checksum: 1e19d0f6e Time (s): cpu = 00:02:01 ; elapsed = 00:01:27 . Memory (MB): peak = 1065.418 ; gain = 45.152 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1e19d0f6e Time (s): cpu = 00:02:01 ; elapsed = 00:01:27 . Memory (MB): peak = 1065.418 ; gain = 45.152 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1e19d0f6e Time (s): cpu = 00:02:01 ; elapsed = 00:01:28 . Memory (MB): peak = 1065.418 ; gain = 45.152 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 2624a9c49 Time (s): cpu = 00:02:02 ; elapsed = 00:01:28 . Memory (MB): peak = 1065.418 ; gain = 45.152 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2624a9c49 Time (s): cpu = 00:02:02 ; elapsed = 00:01:28 . Memory (MB): peak = 1065.418 ; gain = 45.152 Ending Placer Task | Checksum: 191cae780 Time (s): cpu = 00:02:02 ; elapsed = 00:01:28 . Memory (MB): peak = 1065.418 ; gain = 45.152 INFO: [Common 17-83] Releasing license: Implementation 89 Infos, 51 Warnings, 5 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:02:15 ; elapsed = 00:01:35 . Memory (MB): peak = 1065.418 ; gain = 45.152 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 1066.512 ; gain = 1.094 INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/user_35t_wrapper_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 1066.512 ; gain = 1.094 report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.209 . Memory (MB): peak = 1067.418 ; gain = 0.906 report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.316 . Memory (MB): peak = 1067.418 ; gain = 0.000 report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.140 . Memory (MB): peak = 1067.418 ; gain = 0.000 Command: route_design -directive RuntimeOptimized Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: b3aba7bd ConstDB: 0 ShapeSum: de1f3fc3 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 110d3cc1e Time (s): cpu = 00:01:16 ; elapsed = 00:01:02 . Memory (MB): peak = 1183.121 ; gain = 114.223 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 110d3cc1e Time (s): cpu = 00:01:17 ; elapsed = 00:01:03 . Memory (MB): peak = 1183.121 ; gain = 114.223 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 110d3cc1e Time (s): cpu = 00:01:17 ; elapsed = 00:01:04 . Memory (MB): peak = 1183.121 ; gain = 114.223 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 110d3cc1e Time (s): cpu = 00:01:17 ; elapsed = 00:01:04 . Memory (MB): peak = 1183.121 ; gain = 114.223 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1e8f3d527 Time (s): cpu = 00:01:37 ; elapsed = 00:01:16 . Memory (MB): peak = 1202.840 ; gain = 133.941 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.815 | TNS=0.000 | WHS=-0.207 | THS=-221.118| Phase 2 Router Initialization | Checksum: 188383524 Time (s): cpu = 00:01:48 ; elapsed = 00:01:23 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: d595290a Time (s): cpu = 00:02:01 ; elapsed = 00:01:30 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 1010 Number of Nodes with overlaps = 121 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 Phase 4.1.1 Update Timing Phase 4.1.1 Update Timing | Checksum: 123372aee Time (s): cpu = 00:02:29 ; elapsed = 00:01:46 . Memory (MB): peak = 1211.785 ; gain = 142.887 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.423 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 11200b211 Time (s): cpu = 00:02:29 ; elapsed = 00:01:46 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 Phase 4.2.1 Update Timing Phase 4.2.1 Update Timing | Checksum: 1d4f64c84 Time (s): cpu = 00:02:30 ; elapsed = 00:01:47 . Memory (MB): peak = 1211.785 ; gain = 142.887 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.423 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 15dc1952b Time (s): cpu = 00:02:32 ; elapsed = 00:01:48 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 4 Rip-up And Reroute | Checksum: 15dc1952b Time (s): cpu = 00:02:32 ; elapsed = 00:01:48 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 15dc1952b Time (s): cpu = 00:02:32 ; elapsed = 00:01:49 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 15dc1952b Time (s): cpu = 00:02:32 ; elapsed = 00:01:49 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 5 Delay and Skew Optimization | Checksum: 15dc1952b Time (s): cpu = 00:02:32 ; elapsed = 00:01:49 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: dd27f4af Time (s): cpu = 00:02:36 ; elapsed = 00:01:51 . Memory (MB): peak = 1211.785 ; gain = 142.887 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.430 | TNS=0.000 | WHS=0.015 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 101f4108a Time (s): cpu = 00:02:36 ; elapsed = 00:01:51 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 6 Post Hold Fix | Checksum: 101f4108a Time (s): cpu = 00:02:36 ; elapsed = 00:01:51 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 3.17324 % Global Horizontal Routing Utilization = 3.77863 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: dba3c8d8 Time (s): cpu = 00:02:36 ; elapsed = 00:01:51 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: dba3c8d8 Time (s): cpu = 00:02:36 ; elapsed = 00:01:51 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: c3f68e10 Time (s): cpu = 00:02:38 ; elapsed = 00:01:53 . Memory (MB): peak = 1211.785 ; gain = 142.887 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.430 | TNS=0.000 | WHS=0.015 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: c3f68e10 Time (s): cpu = 00:02:38 ; elapsed = 00:01:54 . Memory (MB): peak = 1211.785 ; gain = 142.887 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:02:42 ; elapsed = 00:01:55 . Memory (MB): peak = 1211.785 ; gain = 142.887 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 104 Infos, 51 Warnings, 5 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:02:54 ; elapsed = 00:02:02 . Memory (MB): peak = 1211.785 ; gain = 144.367 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:27 ; elapsed = 00:00:10 . Memory (MB): peak = 1211.785 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/user_35t_wrapper_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:29 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.785 ; gain = 0.000 INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/user_35t_wrapper_drc_routed.rpt. report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.785 ; gain = 0.000 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/user_35t_wrapper_methodology_drc_routed.rpt. report_methodology: Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 1239.586 ; gain = 27.801 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-35] Done setting XDC timing constraints. report_timing_summary: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1243.250 ; gain = 3.664 Command: report_power -file user_35t_wrapper_power_routed.rpt -pb user_35t_wrapper_power_summary_routed.pb -rpx user_35t_wrapper_power_routed.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 114 Infos, 52 Warnings, 5 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 1279.590 ; gain = 36.340 INFO: [Common 17-206] Exiting Vivado at Thu Jun 18 16:35:23 2020... *** Running vivado with args -log user_35t_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source user_35t_wrapper.tcl -notrace ****** Vivado v2016.4 (64-bit) **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017 **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source user_35t_wrapper.tcl -notrace Command: open_checkpoint user_35t_wrapper_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 210.063 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 373 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2016.4 INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37402] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[10]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37472] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[11]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37479] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[12]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37486] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[13]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37493] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[14]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37500] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[15]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37507] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[16]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37514] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[17]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37521] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[18]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37528] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[1]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37409] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[2]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37416] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[3]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37423] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[4]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37430] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[5]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37437] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[6]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37444] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[7]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37451] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[8]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37458] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_a[9]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37465] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_cen[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37613] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37703] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[1]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37710] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[2]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37717] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[3]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37724] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[4]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37731] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[5]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37738] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[6]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37745] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_dq_t[7]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37752] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_oen[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37760] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_emc_0/mem_wen' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_2/user_35t_axi_emc_0_0.edf:37307] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_gpio_0/gpio2_io_i[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_3/user_35t_axi_gpio_0_0.edf:5823] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_uartlite_0/rx' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_7/user_35t_axi_uartlite_0_0.edf:7818] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/axi_uartlite_0/tx' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_7/user_35t_axi_uartlite_0_0.edf:7885] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/clk_wiz_0/reset' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_8/user_35t_clk_wiz_0_0.edf:315] WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'user_35t_i/rst_clk_wiz_0_100M/ext_reset_in' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-12116-Violet/dcp_16/user_35t_rst_clk_wiz_0_100M_0.edf:1546] Parsing XDC File [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-5808-Violet/dcp/user_35t_wrapper_early.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/src/bd/user_35t/ip/user_35t_clk_wiz_0_0/user_35t_clk_wiz_0_0.xdc:57] get_clocks: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 990.609 ; gain = 467.613 Finished Parsing XDC File [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-5808-Violet/dcp/user_35t_wrapper_early.xdc] Parsing XDC File [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-5808-Violet/dcp/user_35t_wrapper_late.xdc] Finished Parsing XDC File [D:/Xilinx/legacy/DigilentOOB/Cmod-A7-35T-OOB/proj/OOB.runs/impl_1/.Xil/Vivado-5808-Violet/dcp/user_35t_wrapper_late.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1005.461 ; gain = 14.828 Restored from archive | CPU: 2.000000 secs | Memory: 0.000000 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1005.461 ; gain = 14.828 INFO: [Project 1-111] Unisim Transformation Summary: A total of 177 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances LUT6_2 => LUT6_2 (LUT6, LUT5): 79 instances RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 58 instances RAM32X1D => RAM32X1D (RAMD32, RAMD32): 32 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540 open_checkpoint: Time (s): cpu = 00:00:51 ; elapsed = 00:00:53 . Memory (MB): peak = 1005.461 ; gain = 795.398 Command: write_bitstream -force -no_partial_bitfile user_35t_wrapper.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 2 threads ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 5 out of 40 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: rgb_led_tri_o[2:0], led_2bits_tri_o[1:0]. ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 5 out of 40 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: rgb_led_tri_o[2:0], led_2bits_tri_o[1:0]. WARNING: [DRC 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1 input user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1 input user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1 input user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1 input user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC 23-20] Rule violation (DPOP-1) PREG Output pipelining - DSP user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1 output user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC 23-20] Rule violation (DPOP-2) MREG Output pipelining - DSP user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1 multiplier stage user_35t_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1/Using_FPGA.DSP48E1_I1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ENBWREN (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[0] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[1] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[2] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[3] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[4] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[5] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[6] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/WEBWE[7] (net: user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/WEBWE[0]) which is driven by a register (user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ENARDEN (net: user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/gpregsm1.curr_fwft_state_reg[1]) which is driven by a register (user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC 23-20] Rule violation (RTSTAT-10) No routable loads - 114 net(s) have no routable loads. The problem bus(es) and/or net(s) are user_35t_i/axi_mem_intercon/s01_couplers/s01_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/s01_couplers/s01_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, user_35t_i/axi_mem_intercon/s01_couplers/s01_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, user_35t_i/axi_mem_intercon/s00_couplers/s00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, user_35t_i/axi_mem_intercon/s01_couplers/s01_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, user_35t_i/axi_mem_intercon/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb (the first 15 of 91 listed). INFO: [Vivado 12-3199] DRC finished with 2 Errors, 18 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation 14 Infos, 53 Warnings, 0 Critical Warnings and 3 Errors encountered. write_bitstream failed write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 1085.629 ; gain = 80.168 ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. INFO: [Common 17-206] Exiting Vivado at Thu Jun 18 16:58:07 2020...