---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 09.12.2019 14:05:06 -- Design Name: -- Module Name: top_level - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Ethernet_tx is Generic ( data_width : positive := 8 ); Port ( clk: in std_logic; rst: in std_logic; enable : in std_logic; data_in : in std_logic_vector(data_width - 1 downto 0); data_num : in std_logic_vector(11 downto 0); header : out std_logic := '0'; payload_flag : out std_logic := '0'; frame_check : out std_logic := '0'; gap : out std_logic:= '0'; tx : out std_logic_vector(1 downto 0) := (others => '0'); txen : out std_logic ); end Ethernet_tx; architecture Behavioral of Ethernet_tx is type state is (preamble_state,start_frame_state,destination_mac_state,source_mac_state,packet_length1_state,packet_length2_state ,payload_state,crc1_state,crc2_state,crc3_state,crc4_state,delay_state); signal current_state : state := preamble_state; signal bit_counter : unsigned(9 downto 0) := (others => '0'); signal delay_counter : unsigned(7 downto 0) :=(others => '0'); constant preamble : std_logic_vector(55 downto 0) := X"55555555555555"; constant start_frame : std_logic_vector(7 downto 0) := X"D5"; constant destination_mac : std_logic_vector(47 downto 0) := X"ffffffffffff"; constant source_mac : std_logic_vector(47 downto 0) := X"FF0FFF0FFF0F"; constant packet_length1 : std_logic_vector(7 downto 0) := X"00"; constant packet_length2 : std_logic_vector(7 downto 0) := X"64"; constant payload : std_logic_vector(655 downto 0) := X"FFFFFFFFFFFFFFFFFF756C20736572656E69FFFFFFFFFFFF2074616B656E2070FFFFFFFFFFFF696F6E206F66206D792065FFFFFFFFFFFF736F756C2C206C696B65207468657365207FFFFFFFFFFFFFFFFFFF"; constant crc1 : std_logic_vector(7 downto 0) := X"2d"; constant crc2 : std_logic_vector(7 downto 0) := X"31"; constant crc3 : std_logic_vector(7 downto 0) := X"33"; constant crc4 : std_logic_vector(7 downto 0) := X"3f"; --interpacket delay is 0.96 us begin sync_proc:process(clk) begin if(rising_edge(clk)) then if(rst = '0') then else txen <= '1'; case(current_state) is when preamble_state => tx(0) <= preamble(to_integer(bit_counter) * 2); tx(1) <= preamble(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 27) then bit_counter <= (others => '0'); current_state <= start_frame_state; else bit_counter <= bit_counter + 1; current_state <= preamble_state; end if; when start_frame_state => tx(0) <= start_frame(to_integer(bit_counter) * 2); tx(1) <= start_frame(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 3) then bit_counter <= (others => '0'); current_state <= destination_mac_state; else bit_counter <= bit_counter + 1; current_state <= start_frame_state; end if; when destination_mac_state => tx(0) <= destination_mac(to_integer(bit_counter) * 2); tx(1) <= destination_mac(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 23) then bit_counter <= (others => '0'); current_state <= source_mac_state; else bit_counter <= bit_counter + 1; current_state <= destination_mac_state; end if; when source_mac_state => tx(0) <= source_mac(to_integer(bit_counter) * 2); tx(1) <= source_mac(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 23) then bit_counter <= (others => '0'); current_state <= packet_length1_state; else bit_counter <= bit_counter + 1; current_state <= source_mac_state; end if; when packet_length1_state => tx(0) <= packet_length1(to_integer(bit_counter) * 2); tx(1) <= packet_length1(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 3) then bit_counter <= (others => '0'); current_state <= packet_length2_state; else bit_counter <= bit_counter + 1; current_state <= packet_length1_state; end if; when packet_length2_state => tx(0) <= packet_length2(to_integer(bit_counter) * 2); tx(1) <= packet_length2(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 3) then bit_counter <= (others => '0'); current_state <= payload_state; else bit_counter <= bit_counter + 1; current_state <= packet_length2_state; end if; when payload_state => tx(0) <= payload(to_integer(bit_counter) * 2); tx(1) <= payload(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 327) then bit_counter <= (others => '0'); current_state <= crc1_state; else bit_counter <= bit_counter + 1; current_state <= payload_state; end if; when crc1_state => tx(0) <= crc1(to_integer(bit_counter) * 2); tx(1) <= crc1(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 3) then bit_counter <= (others => '0'); current_state <= crc2_state; else bit_counter <= bit_counter + 1; current_state <= crc1_state; end if; when crc2_state => tx(0) <= crc2(to_integer(bit_counter) * 2); tx(1) <= crc2(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 3) then bit_counter <= (others => '0'); current_state <= crc3_state; else bit_counter <= bit_counter + 1; current_state <= crc2_state; end if; when crc3_state => tx(0) <= crc3(to_integer(bit_counter) * 2); tx(1) <= crc3(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 3) then bit_counter <= (others => '0'); current_state <= crc4_state; else bit_counter <= bit_counter + 1; current_state <= crc3_state; end if; when crc4_state => tx(0) <= crc4(to_integer(bit_counter) * 2); tx(1) <= crc4(1 + (to_integer(bit_counter) * 2)); if(bit_counter = 3) then bit_counter <= (others => '0'); current_state <= delay_state; else bit_counter <= bit_counter + 1; current_state <= crc4_state; end if; when delay_state => tx <= "00"; txen <= '0'; if(delay_counter = 47) then delay_counter <= (others => '0'); current_state <= preamble_state; else delay_counter <= delay_counter + 1; current_state <= delay_state; end if; when others => end case; end if; end if; end process; end Behavioral;