---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 09/24/2016 01:16:29 PM -- Design Name: -- Module Name: read - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use IEEE.std_logic_arith.all; USE ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity write_read is generic ( START1 : std_logic_vector(2 downto 0) :="000"; START2 : std_logic_vector(2 downto 0) :="001"; START3 : std_logic_vector(2 downto 0) :="010"; START4 : std_logic_vector(2 downto 0) :="011"; START5 : std_logic_vector(2 downto 0) :="100"; START6 : std_logic_vector(2 downto 0) :="101"; START7 : std_logic_vector(2 downto 0) :="110" ); port ( sys_clk_p : in std_logic; sys_clk_n : in std_logic; reset : in std_logic; ddr3_dq : inout std_logic_vector(7 downto 0); ddr3_dqs_p : inout std_logic_vector(0 downto 0); ddr3_dqs_n : inout std_logic_vector(0 downto 0); ddr3_addr : out std_logic_vector(14 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_odt : out std_logic_vector(0 downto 0); led : out std_logic_vector(7 downto 0) -- VGA_HS_O : out STD_LOGIC; -- VGA_VS_O : out STD_LOGIC; -- VGA_RED_O : out STD_LOGIC_VECTOR (4 downto 0); -- VGA_BLUE_O : out STD_LOGIC_VECTOR (4 downto 0); -- VGA_GREEN_O : out STD_LOGIC_VECTOR (5 downto 0) ); end write_read; architecture Behavioral of write_read is component mig_7series_0 port ( ddr3_dq : inout std_logic_vector(7 downto 0); ddr3_dqs_p : inout std_logic_vector(0 downto 0); ddr3_dqs_n : inout std_logic_vector(0 downto 0); ddr3_addr : out std_logic_vector(14 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_odt : out std_logic_vector(0 downto 0); app_addr : in std_logic_vector(28 downto 0); app_cmd : in std_logic_vector(2 downto 0); app_en : in std_logic; app_wdf_data : in std_logic_vector(63 downto 0); app_wdf_end : in std_logic; app_wdf_wren : in std_logic; app_rd_data : out std_logic_vector(63 downto 0); app_rd_data_end : out std_logic; app_rd_data_valid : out std_logic; app_rdy : out std_logic; app_wdf_rdy : out std_logic; app_sr_req : in std_logic; app_ref_req : in std_logic; app_zq_req : in std_logic; app_sr_active : out std_logic; app_ref_ack : out std_logic; app_zq_ack : out std_logic; ui_clk : out std_logic; ui_clk_sync_rst : out std_logic; init_calib_complete : out std_logic; -- System Clock Ports sys_clk_p : in std_logic; sys_clk_n : in std_logic; sys_rst : in std_logic ); end component mig_7series_0; component clk_wiz_0 port (-- Clock in ports clk_in1 : in std_logic; -- Clock out ports clk_out1 : out std_logic; -- Status and control signals resetn : in std_logic; locked : out std_logic ); end component; COMPONENT ila_0 PORT ( clk : IN STD_LOGIC; probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT ; signal app_addr : std_logic_vector(28 downto 0); signal app_cmd : std_logic_vector(2 downto 0):= (others=>'0'); signal app_en : std_logic:= '0'; signal app_rdy : std_logic:= '0'; signal app_rd_data : std_logic_vector(63 downto 0); signal app_rd_data_temp : std_logic_vector(63 downto 0); signal app_rd_data_end : std_logic; signal app_rd_data_valid : std_logic; signal app_rd_data_valid_o : std_logic; signal app_wdf_data : std_logic_vector(63 downto 0):= (others=>'0'); signal app_wdf_end : std_logic := '0'; signal app_wdf_rdy : std_logic; signal app_sr_active : std_logic; signal app_ref_ack : std_logic; signal app_zq_ack : std_logic; signal app_wdf_wren : std_logic :='0'; signal ui_clk : std_logic; signal ui_clk_sync_rst : std_logic; signal init_calib_complete : std_logic; signal state : std_logic_vector(2 downto 0); signal locked : std_logic; signal wr_done_r : std_logic; signal user_burst_done : std_logic; signal wr_do_it : std_logic; signal wr_read : std_logic; signal w_clk : std_logic; signal counter_w : std_logic_vector (1 downto 0):= (others => '0'); signal counter_i : std_logic_vector (1 downto 0):= (others => '0'); signal counter_r : std_logic_vector (1 downto 0):= (others => '0'); signal state_w_1 : std_logic_vector (2 downto 0); signal led1 : std_logic_vector(7 downto 0); begin process (ui_clk) begin state<= START1; if (reset='0') then led<= X"FF"; elsif rising_edge (ui_clk) then --if(clk'event and clk='1') then case state is when START1 => led<= X"01"; counter_w<= (others => '0'); app_cmd <= "000"; app_addr<= "00000000000000000000011111111"; app_en<= '1'; state <= START2; when START2 => if (app_rdy = '1')and (app_wdf_rdy='1') then if (counter_w < "10") then counter_w<= counter_w+'1'; else led<= X"02"; state <= START3; end if; end if; -- when START3 => if (app_rdy = '1') and (app_wdf_rdy='1') then app_wdf_data <= X"AAAAAAAAAAAAAAAA"; app_wdf_wren <='1'; app_wdf_end <='1'; led<= X"03"; counter_i<= (others => '0'); state <= START4; end if; when START4 => if (counter_i < "10") then counter_i<= counter_i+'1'; else led<= X"03"; app_en<= '0'; app_wdf_wren <='0'; app_wdf_end <='0'; counter_r<= (others => '0'); state <= START5; end if; when START5 => if (counter_r < "10") then counter_r<= counter_r+'1'; else led<= X"04"; app_cmd <= "001"; app_addr<= "00000000000000000000011111111"; app_en<= '1'; state <= START6; end if; when START6 => if (app_rdy = '1') and (app_rd_data_valid = '1') then led<= X"05"; app_rd_data_temp <= app_rd_data ; end if; when others => led<= X"06"; end case; end if; end process; clk_108: clk_wiz_0 port map ( -- Clock in ports clk_in1 => ui_clk, -- Clock out ports clk_out1 => w_clk, -- Status and control signals resetn => reset, locked => locked ); MIG_IP: mig_7series_0 port map ( -- Memory interface ports ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, init_calib_complete => init_calib_complete, ddr3_cs_n => ddr3_cs_n, ddr3_odt => ddr3_odt, -- Application interface ports app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_sr_req => '0', app_ref_req => '0', app_zq_req => '0', app_sr_active => app_sr_active, app_ref_ack => app_ref_ack, app_zq_ack => app_zq_ack, ui_clk => ui_clk, ui_clk_sync_rst => ui_clk_sync_rst, -- System Clock Ports sys_clk_p => sys_clk_p, sys_clk_n => sys_clk_n, sys_rst => reset ); logic_analyzer: ila_0 PORT MAP ( clk => ui_clk, probe0 (0)=> reset, probe1 (0)=> ui_clk_sync_rst ); --//led<= X"0F"; end Behavioral;