---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:52:26 09/02/2016 -- Design Name: -- Module Name: disp - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; library ieee_proposed; use ieee_proposed.fixed_pkg.all; --use ieee.fixed_generic_pkg.all; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity disp is -- Target digit refreshing frequency is 125 Hz; -- with 8 digits (SSD's) the whole display must be rfreshed at 125*8Hz; -- 125*8=1kHz; -- to convert 100mhz clk into 1 khz the clk_divider must be 100'000; -- hence count from 0 to 49'999 and togle the clock signal generic ( M_clk : integer;-- := 49999; Mi : integer;-- := 4; -- num of bits for integer part Mf : integer;-- := 7; -- num of bits for fractional part res : ufixed (0 downto -16));-- := "00000000000101000"); Port ( clk100mhz : in STD_LOGIC; an : out STD_LOGIC_VECTOR (7 downto 0); -- common anodes LOW ca : out std_logic; -- top cb : out std_logic; -- top-right cc : out std_logic; -- bottom-right cd : out std_logic; -- bottom ce : out std_logic; -- bottom-left cf : out std_logic; -- top-left cg : out std_logic; -- middle dp : out std_logic; -- decimal point data2disp : in std_logic_vector (11 downto 0) -- data to be displayed (from FuncGen) ); end disp; architecture Behavioral of disp is -- Display refresh clock signal signal clk1khz : std_logic; -- SSD selector signal count_ssd : integer range 0 to 7 := 0; -- Logic vector, containing BCD for both integer and fractional parts signal digits : std_logic_vector (31 downto 0);-- 4int+28fract -- Array to store control output signals for SSD's type array_type is array (0 to 7) of std_logic_vector (6 downto 0); signal ssd_dig : array_type := (others => (others => '0')); -- Data conversion part -- signal to store data to be displayed in unsigned format signal adc_ufixed : ufixed (11 downto 0) := (others => '0'); -- actual feedback signal in Volts in unsigned format signal volt_adc : ufixed (12 downto -16) := (others => '0'); -- Truncated feedback signal, representing feedback signal in Volts in STD_LOGIC_Vector format signal data_disp : std_logic_vector (10 downto 0) := (others => '0'); -- Instantiation of the Display components component clock generic ( M_clk: integer); -- display clock divisor port ( clk100mhz : in STD_LOGIC; -- board clock clk_disp : out STD_LOGIC);-- display clock end component; -- Seven Segment Display component ssd port ( clk100mhz : in STD_LOGIC; -- board clock bcd : in STD_LOGIC_VECTOR (3 downto 0); -- binary-coded-decimal (BCD) to be displayed by SSD segment : out STD_LOGIC_VECTOR (6 downto 0)); -- SSD's control outputs end component; -- Converter of the Binary to BCD number for integer part component ibin2bcd generic ( Mi : integer); -- number of bits for integer part port ( clk100mhz : in STD_LOGIC; -- board clock idata2conv : in STD_LOGIC_VECTOR (3 downto 0); -- binary number to be converted conv_datai : out STD_LOGIC_VECTOR (3 downto 0)); -- converted (BCD) number end component; -- Converter of the Binary to BCD number for fractional part component fbin2bcd generic ( Mf : integer); -- number of bits for fractional part port ( clk100mhz : in STD_LOGIC; -- board clock fdata2conv : in STD_LOGIC_VECTOR (6 downto 0); -- binary number to be converted conv_dataf : out STD_LOGIC_VECTOR (27 downto 0));-- converted (BCD) number end component; begin -- Connection between formal and actual signals DISP_CLK: clock generic map ( M_clk => M_clk) -- pass display clock divisor value to Clock module port map ( clk100mhz => clk100mhz,-- connect clock input to Clock module clk_disp => clk1khz); -- return clock signal from Display module IntB2BCD: ibin2bcd generic map (Mi => Mi) -- pass number of bits for integer part to Binary-to-BCD converter port map ( clk100mhz => clk100mhz,-- connect clock input to Binary-to-BCD converter idata2conv => data_disp(10 downto 7),-- pass binary number to be converted to Binary-to-BCD converter conv_datai => digits(31 downto 28)); -- return conversion results from Binary-to-BCD converter FractB2BCD: fbin2bcd generic map (Mf => Mf) -- pass number of bits for fractional part to Binary-to-BCD converter port map ( clk100mhz => clk100mhz, -- connect clock input to Binary-to-BCD converter fdata2conv => data_disp(6 downto 0),-- pass binary number to be converted to Binary-to-BCD converter conv_dataf => digits(27 downto 0)); -- return conversion results from Binary-to-BCD converter -- SSD instance for integer part SSD0: ssd -- For this and others SSD modules: port map ( clk100mhz => clk100mhz, -- connect clock input to SSD module bcd => digits(31 downto 28),-- pass 4 bits of BCD to SSD module to encode its value into SSD's control sequence segment => ssd_dig(0)); -- return SSD's control sequence to Display module -- SSD instances for fractional part SSD1: ssd port map ( clk100mhz => clk100mhz, bcd => digits(27 downto 24), segment => ssd_dig(1)); SSD2: ssd port map ( clk100mhz => clk100mhz, bcd => digits(23 downto 20), segment => ssd_dig(2)); SSD3: ssd port map ( clk100mhz => clk100mhz, bcd => digits(19 downto 16), segment => ssd_dig(3)); SSD4: ssd port map ( clk100mhz => clk100mhz, bcd => digits(15 downto 12), segment => ssd_dig(4)); SSD5: ssd port map ( clk100mhz => clk100mhz, bcd => digits(11 downto 8), segment => ssd_dig(5)); SSD6: ssd port map ( clk100mhz => clk100mhz, bcd => digits(7 downto 4), segment => ssd_dig(6)); SSD7: ssd port map ( clk100mhz => clk100mhz, bcd => digits(3 downto 0), segment => ssd_dig(7)); disp_num: process (clk1khz) begin if(rising_edge(clk1khz)) then case count_ssd is -- progressively update SSD's (from left to right) with conversion results when 0 => -- 0's SSD an <= "01111111"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '0'; count_ssd <= count_ssd+1; when 1 => -- 1st SSD an <= "10111111"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '1'; count_ssd <= count_ssd+1; when 2 => -- 2nd SSD and DP an <= "11011111"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '1'; count_ssd <= count_ssd+1; when 3 => -- 3rd SSD an <= "11101111"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '1'; count_ssd <= count_ssd+1; when 4 => -- 4th SSD an <= "11110111"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '1'; count_ssd <= count_ssd+1; when 5 => -- 5th SSD an <= "11111011"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '1'; count_ssd <= count_ssd+1; when 6 => -- 6th SSD an <= "11111101"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '1'; count_ssd <= count_ssd+1; when 7 => -- 7th SSD an <= "11111110"; ca <= ssd_dig(count_ssd) (6); cb <= ssd_dig(count_ssd) (5); cc <= ssd_dig(count_ssd) (4); cd <= ssd_dig(count_ssd) (3); ce <= ssd_dig(count_ssd) (2); cf <= ssd_dig(count_ssd) (1); cg <= ssd_dig(count_ssd) (0); dp <= '1'; count_ssd <= 0; end case; end if; end process disp_num; -- this process converts feedback signal (std_logic_vector) into -- feedback voltage value (std_logic_vector as well). One part of the new signal represents -- integer part and another part is for the fractional part display_adc: process (clk100mhz, data2disp, adc_ufixed, volt_adc, data_disp) begin adc_ufixed <= to_ufixed(unsigned(data2disp)); -- convert input to ufixed (11 to 0) xxxx'xxxx'xxxx. volt_adc <= adc_ufixed*res; -- xxxx'xxxx'xxxx.*0.0000'0000'0010'1000=x'xxxx'xxxx'xxxx.xxxx'xxxx'xxxx'xxxx data_disp <= std_logic_vector(unsigned(volt_adc(3 downto -7)));-- truncate xxxx.xxxx'xxx and convert -- max value for integer part is 2, hence 4 bit is enough; -- 7 SSD's for fractional part, hence 2^-7 is the smallest number that can be displayed end process display_adc; end Behavioral;