`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// //Kaushik ////////////////////////////////////////////////////////////////////////////////// module main (imf1,clk,rst,en); input clk,rst,en; output wire signed [15:0] imf1; wire signed [15:0] re1; //wire signed [15:0] re2; reg signed [15:0] in; wire clk_out; //reg signed [15:0] mem; //reg signed [15:0] mem1; //reg signed [15:0] mem2; //ila_0 debug0 (.clk(clk), .probe0(imf1)); ////////////////////////////delay of clk/////////////// clock_divi ccl(clk,clk_out); mod_imf_one mi1 (in,imf1,clk_out,rst,en,re1); reg signed [15:0]mydata[1:2499]; integer i=0; initial $readmemh("C:\\Users\\KK-HP\\Desktop\\emd_clean_01_10_2018\\cosinee.txt",mydata); always @(posedge clk_out) begin if(rst) begin in=0; end else begin in=mydata[i]; i=i+1; end end endmodule