`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 05/15/2019 06:03:32 PM
// Design Name: 
// Module Name: Com
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Com(

    input clk,
    input Rx,
    output reg Tx,

    output reg led0,
    output reg led1,
    output reg led2,
    output reg led3    
   );
  
	reg clk1;
	reg tx_reg;
	reg [2:0] transfer_bit_count;
 
  	reg flag;
  	reg signed [7:0]counter ;
  	reg temp;
  	reg [7:0] received_byte;
  	reg byte_ready;
  
 	 reg [12:0] baud_rate_clock = 0;
 	 reg [12:0] baud_rate_clock1 = 0;

 	 reg baud_tick;
  	 reg baud_tick1=1'b0;

  	reg [7:0] shift_reg;
  	reg [4:0]state;
  
  
   initial 
              begin
              	 clk1 <=0;
              	 led0<=0;
//	      	 led1<=0;
//	      	 led2<=0;
//              	 led3<=0;
             state = IDLE;
             counter = 0;
             flag = 0;
             shift_reg <= 0;
             transfer_bit_count<=0;
             Tx <= 1;
              end
      
parameter         IDLE  =   4'd0, 
                  START =   4'd1, 
                  BIT_0 =   4'd2,
                  BIT_1 =   4'd3,
                  BIT_2 =   4'd4,
                  BIT_3 =   4'd5,
                  BIT_4 =   4'd6,
                  BIT_5 =   4'd7,  
                  BIT_6 =   4'd8,                                                                     
                  BIT_7 =   4'd9,
                  STOP =    4'd10;
    
//slow_clock1

      always @(posedge clk)
       begin
            if (baud_rate_clock == 13'd25000000) 
            begin
              baud_rate_clock <= 0;
              baud_tick <= ~baud_tick;
            end
            else 
            begin
           baud_rate_clock = baud_rate_clock + 13'd1;
            end 
      end
      
  //slow_clock2

      always @(posedge clk)
       begin
            if (baud_rate_clock1 == 13'd900) 
            begin
              baud_rate_clock1 <= 0;
              baud_tick1 <= ~baud_tick1;
            end
            
            else 
            begin
              baud_rate_clock1 = baud_rate_clock1 + 13'd1;
            end
      end
      
      
      //Uart_Logic
      
      
        always @(posedge baud_tick1) 
         begin
//             if(counter == 0 && flag  ==  0)
//             begin
//                 counter <= counter + 1;
//             end
//             else if(counter == 1 && flag  ==  0)
//                 begin
//                     counter <= counter + 1;
//                 end
//             else if(counter == 2 && flag  ==  0)
//                 begin
//                     counter <= counter + 1;
//                 end
//              else if(counter == 3 && flag  ==  0)
//                 begin
//                     counter <= 0;
//                     flag <= 1;
//                 end
//             else if (counter <= 7 && flag == 1)
//             begin
//              counter <= counter + 1;
//              end
//             else if(counter == 8 && flag == 1)
//             begin 
//            led0 <=1;
            
             case(state)
                        IDLE:
                        begin
                           byte_ready <= 0;
                           if(Tx == 1)
                           begin
                                state <= BIT_0;
                           end
//                           led0<=1;
                         end

                    START: 
                        begin
                           Tx <= 0;
//                           led1<=1;
                           state <= BIT_0;
                       end

                        BIT_0: 
                        begin
                               Tx <= 1;
//                               led2<=1;
                               state<= BIT_1;
                           end

                        BIT_1: 
                        begin
                               Tx <= 1;
//                               led0<=1;
                               state<= BIT_2;
                        end
                    
                        BIT_2: 
                        begin
                               Tx <= 1;
//                               led1<=1;
                               state<= BIT_3;
                           end                    
                    
                        BIT_3: 
                           begin
                                  Tx <= 1;
//                                  led2<=1;
                                  state<= BIT_4;
                              end
   
                           BIT_4: 
                           begin
                                  Tx <= 0;
//                                  led0<=1;
                                  state<= BIT_5;
                           end
                       
                           BIT_5: 
                           begin
                                  Tx <= 0;
//                                  led1<=1;
                                  state<= BIT_6;
                              end   
                              
                           BIT_6: 
                              begin
                                     Tx <= 0;
//                                     led0<=1;
                                     
                                     state<= BIT_7;
                              end
                          
                              BIT_7: 
                              begin
                                     Tx <= 0;
//                                     led1<=1;
                                     state<= STOP;
                                 end                               
                                               
                            STOP: 
                            begin
                                    state <= IDLE;
                                    byte_ready <= 1;
                                    Tx <= 1;
//                                   led3<=1;
                            end
                    
                        default:
                        begin
                            state <= IDLE;
//                           led0<=0;
//                           led1<=0;
//                           led2<=0;
//                           led3<=0;
                       end
                    endcase 

               
             if(byte_ready == 1)
             begin
		            led0<=1;
//                   led1<=1;
//                   led2<=1;
//                   led3<=1;              
              end
       else 
       begin
                  counter <= 0;
                  end
//   Tx<=tx_reg;      
  end  
 
endmodule