`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 05/02/2019 07:43:39 PM
// Design Name: 
// Module Name: addsub_8bit_cascade4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module addsub_8bit_cascade4(cout, s, a, b, cin);
    output cout;                 
    output [7:0] s;
    input [7:0] a;
    input [7:0] b;
    input cin;                                      
    
    wire [2:1] carry;  
    wire op;
    
    assign op = cin;            
   
    addsub_4bit nibble0(carry[1], s[3:0], a[3:0], b[3:0], cin, op);
    addsub_4bit nibble1(carry[2], s[7:4], a[7:4], b[7:4], carry[1], op);

    assign cout = carry[2];    // final carry out (carry[2] assigned to cout   

endmodule

module addsub_4bit(cout, s, a, b, cin, op);
    output cout;                 
    output [3:0] s;
    input [3:0] a;
    input [3:0] b;
    input cin;
    input op;                     

    wire [3:0] bin;                
    assign bin[0] = b[0]^op;
    assign bin[1] = b[1]^op;
    assign bin[2] = b[2]^op;
    assign bin[3] = b[3]^op;
    
    wire [4:1] carry;         
    
     // instantiation parameters: full_adder(cout, s, a, b, cin)
     full_adder FA0(carry[1],s[0],a[0],bin[0],cin);
     full_adder FA1(carry[2],s[1],a[1],bin[1],carry[1]);
     full_adder FA2(carry[3],s[2],a[2],bin[2],carry[2]);
     full_adder FA3(carry[4],s[3],a[3],bin[3],carry[3]);

    assign cout = cin ^ carry[4];

endmodule

module full_adder(cout, s, a, b, cin);
    output cout;
    output s;
    input a;
    input b;
    input cin;
    
    wire w1, w2, w3;
    
    xor(w1,a,b);
    xor(s,w1,cin);
    and(w2,a,b);
    and(w3,w1,cin);
    or(cout,w3,w2);

endmodule