library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
  port (
    dphy_clk_lp_n_0 : in STD_LOGIC;
    dphy_clk_lp_p_0 : in STD_LOGIC;
    dphy_data_hs_n_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_hs_p_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_n_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_p_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_hs_clock_0_clk_n : in STD_LOGIC;
    dphy_hs_clock_0_clk_p : in STD_LOGIC;
    m_axis_video_0_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 );
    m_axis_video_0_tlast : out STD_LOGIC;
    m_axis_video_0_tready : in STD_LOGIC;
    m_axis_video_0_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_video_0_tvalid : out STD_LOGIC;
    reset_rtl : in STD_LOGIC;
    reset_rtl_0 : in STD_LOGIC;
    sys_clock : in STD_LOGIC
  );
end design_1_wrapper;

architecture STRUCTURE of design_1_wrapper is
  component design_1 is
  port (
    sys_clock : in STD_LOGIC;
    reset_rtl : in STD_LOGIC;
    reset_rtl_0 : in STD_LOGIC;
    m_axis_video_0_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 );
    m_axis_video_0_tlast : out STD_LOGIC;
    m_axis_video_0_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_video_0_tvalid : out STD_LOGIC;
    m_axis_video_0_tready : in STD_LOGIC;
    dphy_hs_clock_0_clk_p : in STD_LOGIC;
    dphy_hs_clock_0_clk_n : in STD_LOGIC;
    dphy_clk_lp_p_0 : in STD_LOGIC;
    dphy_clk_lp_n_0 : in STD_LOGIC;
    dphy_data_hs_p_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_hs_n_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_p_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_n_0 : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  end component design_1;
begin
design_1_i: component design_1
     port map (
      dphy_clk_lp_n_0 => dphy_clk_lp_n_0,
      dphy_clk_lp_p_0 => dphy_clk_lp_p_0,
      dphy_data_hs_n_0(1 downto 0) => dphy_data_hs_n_0(1 downto 0),
      dphy_data_hs_p_0(1 downto 0) => dphy_data_hs_p_0(1 downto 0),
      dphy_data_lp_n_0(1 downto 0) => dphy_data_lp_n_0(1 downto 0),
      dphy_data_lp_p_0(1 downto 0) => dphy_data_lp_p_0(1 downto 0),
      dphy_hs_clock_0_clk_n => dphy_hs_clock_0_clk_n,
      dphy_hs_clock_0_clk_p => dphy_hs_clock_0_clk_p,
      m_axis_video_0_tdata(39 downto 0) => m_axis_video_0_tdata(39 downto 0),
      m_axis_video_0_tlast => m_axis_video_0_tlast,
      m_axis_video_0_tready => m_axis_video_0_tready,
      m_axis_video_0_tuser(0) => m_axis_video_0_tuser(0),
      m_axis_video_0_tvalid => m_axis_video_0_tvalid,
      reset_rtl => reset_rtl,
      reset_rtl_0 => reset_rtl_0,
      sys_clock => sys_clock
    );
end STRUCTURE;