library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Filter is
    Port ( stm : in STD_LOGIC_VECTOR (3 downto 0);
            ld1: out STD_LOGIC;
            ld2: out STD_LOGIC;
            ld3: out STD_LOGIC;
            ld4: out STD_LOGIC
           );
end Filter;

architecture Behavioral of Filter is
  --signal ts : std_logic_vector( 1 downto 0) := "01";
  
begin
    ld1 <= stm(0);
    ld2 <= stm(1);
    ld3 <= stm(2);
    ld4 <= stm(3);
   
end Behavioral;