`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 04/14/2019 12:55:13 PM
// Design Name: 
// Module Name: Multiple_bits
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Multiple_bits(
     input clk,
    input [31:0] din,
    output reg  [3:0] web,
    output reg en,
    output reg rstb,
    output reg [31:0] addr,
    output reg led0,
    output reg led1,
    output reg led2,
    output reg led3

    );
    
integer i;

    initial begin
        rstb <= 0;
        en <= 1;
        web <= 4'b0000;
        i <= 0;
    end

always@(posedge clk)
    begin
        if(i == 0)
        begin
            addr <= 32'h40000000 + i;
			led0 <= din[0];
        end
		else if (i == 1)
		begin
            addr <= 32'h40000000 + i;
			led1 <= din[0];			
		end
		else if (i == 2)
		begin
            addr <= 32'h40000000 + i;
			led2 <= din[0];			
		end
			else if (i == 3)
		begin
            addr <= 32'h40000000 + i;
			led3 <= din[0];			
		end
		i <= i+1;
    end

endmodule