---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:17:57 03/07/2019 -- Design Name: -- Module Name: Counter_Module - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity CounterDesign_withFIFO_DCM is generic(N: integer :=16); Port (Clock: in std_logic; --Reset : in std_logic:='0'; Counter_enable:in std_logic; Counter_disable:in std_logic; Anode_Activate :out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals LED_out :out STD_LOGIC_VECTOR (6 downto 0) ); end CounterDesign_withFIFO_DCM; architecture Behavioral of CounterDesign_withFIFO_DCM is signal count: Std_Logic_Vector(N-1 downto 0):= (others => '0'); signal max_ticks:Std_Logic_Vector(1 downto 0):="00"; constant ovfvalue:Std_Logic_Vector(N-1 downto 0) := (others => '1');--max value 65535 for 16 bit count signal constant clkperiod:Std_Logic_Vector(4 downto 0) := "10100";--("10100"-20ns) signal cebuffer:Std_Logic:='0'; signal Activate:Std_Logic:='0'; signal Counterout:std_logic_vector(2*N-1 downto 0):=(others => '0'); signal LED_activating_counter:Std_Logic_Vector(1 downto 0); signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0):=(others => '0'); signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0); signal displayed_number: STD_LOGIC_VECTOR (15 downto 0); -----------Signals Required for DCM are given below------------ signal clk : std_logic; -----------Signals Required for FIFO are given below------------ signal clk_sap : std_logic; signal cnt : integer range 0 to 1000;--std_logic_vector(9 downto 0); signal data : std_logic_vector(31 downto 0);--:="0000000000111111"; signal dataout : std_logic_vector(31 downto 0); signal empty : std_logic; signal full : std_logic; signal wr_en : std_logic; signal rd_en : std_logic; signal write_reg : std_logic; signal read_reg : std_logic; signal FiFO_Activate_write:Std_Logic; signal FiFO_Activate_read:Std_Logic; COMPONENT DCM_200Mhz PORT( CLKIN_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic ); END COMPONENT; COMPONENT Async_fifo_dcm PORT ( wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC); END COMPONENT; begin Inst_DCM_200Mhz: DCM_200Mhz PORT MAP( CLKIN_IN => Clock, CLKFX_OUT => clk, CLKIN_IBUFG_OUT => open, CLK0_OUT => open ); process(LED_BCD) begin case LED_BCD is when "0000" => LED_out <= "0000001"; -- "0" when "0001" => LED_out <= "1001111"; -- "1" when "0010" => LED_out <= "0010010"; -- "2" when "0011" => LED_out <= "0000110"; -- "3" when "0100" => LED_out <= "1001100"; -- "4" when "0101" => LED_out <= "0100100"; -- "5" when "0110" => LED_out <= "0100000"; -- "6" when "0111" => LED_out <= "0001111"; -- "7" when "1000" => LED_out <= "0000000"; -- "8" when "1001" => LED_out <= "0000100"; -- "9" when "1010" => LED_out <= "0000010"; -- a when "1011" => LED_out <= "1100000"; -- b when "1100" => LED_out <= "0110001"; -- C when "1101" => LED_out <= "1000010"; -- d when "1110" => LED_out <= "0110000"; -- E when "1111" => LED_out <= "0111000"; -- F when others => LED_out <= (others => '1'); end case; end process; process(LED_activating_counter) begin case LED_activating_counter is when "00" => Anode_Activate <= "0111"; -- activate LED1 and Deactivate LED2, LED3, LED4 LED_BCD <= displayed_number(15 downto 12); -- the first hex digit of the 16-bit number when "01" => Anode_Activate <= "1011"; -- activate LED2 and Deactivate LED1, LED3, LED4 LED_BCD <= displayed_number(11 downto 8); -- the second hex digit of the 16-bit number when "10" => Anode_Activate <= "1101"; -- activate LED3 and Deactivate LED2, LED1, LED4 LED_BCD <= displayed_number(7 downto 4); -- the third hex digit of the 16-bit number when "11" => Anode_Activate <= "1110"; -- activate LED4 and Deactivate LED2, LED3, LED1 LED_BCD <= displayed_number(3 downto 0); -- the fourth hex digit of the 16-bit number when others => Anode_Activate <= "1111"; LED_BCD <= "0000"; end case; end process; process(clk) begin if(rising_edge(clk)) then if(Counter_enable='1' and cebuffer='0' and Counter_disable='0') then cebuffer <='1'; count<=(others => '0'); FiFO_Activate_write<='0'; --FiFO_Activate_read<='0'; end if; if(cebuffer='1' and Counter_disable='0')then --(Counter_enable='1' and Counter_disable='0' if(count<2**N-1)then --check for counter overflow before incrementing the counter count<=count+1; --increment the counter elsif(count=2**N-1)then max_ticks <= max_ticks + 1 ; count<=(0 => '1', others => '0');--start the count process again end if; elsif(cebuffer='1' and Counter_disable='1') then --Counterout<=(Counterout'range => '0') +(std_logic_vector(count+(max_ticks*unsigned(ovfvalue))))*clkperiod; --Counterout<=(Counterout'range => '0') +((count+(max_ticks*ovfvalue))*clkperiod); Counterout<=(Counterout'range => '0')+(count); cebuffer<='0'; FiFO_Activate_write<='1'; end if; end if; end process; process(clk) begin if (rising_edge(clk)) then write_reg <= FiFO_Activate_write; read_reg<= empty; end if; end process; --/////////////Ctrl////////////////////// process(FiFO_Activate_write,write_reg,empty,read_reg) begin if (FiFO_Activate_write = '1' and write_reg = '0') then data<=Counterout; wr_en <= '1';--wr_en is enabled,after write executed rd_en <= '0'; elsif(empty<='0' and read_reg = '1') then --falling edge of FiFO_Activate_read wr_en <= '0';--wr_en is disabled rd_en <= '1';--and rd_en is enabled Activate<='1'; end if; end process; process(dataout,Activate) begin displayed_number<=Counterout(15 downto 0); if(rising_edge(clk))then refresh_counter <= refresh_counter + 1; end if; end process; --LED_activating_counter<= refresh_counter(19 downto 18); LED_activating_counter<= "11"; --/////////////////div_1000///////////////////// process(clk,cnt)--this process generats a clock of 50K Hz begin if (clk'event and clk = '1') then if (cnt < 999) then cnt <= cnt + 1; else cnt <= 0;--"0000000000"; end if; end if; if (cnt < 500) then clk_sap <= '0'; else clk_sap <= '1'; end if; end process; --///////////////Inst//////////////////////// FIFO : Async_fifo_dcm PORT MAP ( wr_clk => clk_sap, rd_clk => clk, din => data, wr_en => wr_en, rd_en => rd_en, dout => dataout, empty => empty, full => full); end Behavioral;